This paper describes an investigation of cosmic-ray-induced multicell error behavior in SRAMs. A combination of device- and circuit-level simulation was used to show that a parasitic bipolar effect is responsible for such errors, and the underlying mechanism is what we call a battery effect. We have also demonstrated, for the first time, that the maximum number of cell errors per cosmic-ray strike depends on the number of cells between well taps (Nc). The results are used as the basis of an error checking and correction (ECC) design guideline for the handling of cosmic-ray-induced multicell errors. The proposed guideline simply states that the allocation of memory cells to addresses should be based on consideration of the Nc. The architecture in its form reduces the soft error rate of an SRAM with Nc=16 by 88%.