Sampling error minimization using a differential bootstrapped sampler
D Jakonis, C Svensson - Swedish System-on-Chip Conference 2001 …, 2001 - diva-portal.org
Swedish System-on-Chip Conference 2001, Arild, Sweden. 20-21/3 2001, 2001•diva-portal.org
This paper presents a novel bootstrap technique implemented in a fully-differential sampler.
The main sampling errors are discussed and the sampling time variation for the
bootstrapped sampler is derived. The proposed bootstrap sampler is compared with an
ordinary sampler to show an improvement in SFDR. A differential clock sampling is
introduced to minimize the sampling error due to noise in clock and power supply.
Simulation results show significant improvement in sampling accuracy.
The main sampling errors are discussed and the sampling time variation for the
bootstrapped sampler is derived. The proposed bootstrap sampler is compared with an
ordinary sampler to show an improvement in SFDR. A differential clock sampling is
introduced to minimize the sampling error due to noise in clock and power supply.
Simulation results show significant improvement in sampling accuracy.
This paper presents a novel bootstrap technique implemented in a fully-differential sampler. The main sampling errors are discussed and the sampling time variation for the bootstrapped sampler is derived. The proposed bootstrap sampler is compared with an ordinary sampler to show an improvement in SFDR. A differential clock sampling is introduced to minimize the sampling error due to noise in clock and power supply. Simulation results show significant improvement in sampling accuracy.
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