System architecture directions for post-soc/32-bit networked sensors

HS Kim, MP Andersen, K Chen, S Kumar… - Proceedings of the 16th …, 2018 - dl.acm.org
Proceedings of the 16th ACM conference on embedded networked sensor systems, 2018dl.acm.org
The emergence of low-power 32-bit Systems-on-Chip (SoCs), which integrate a 32-bit MCU,
radio, and flash, presents an opportunity to re-examine design points and trade-offs at all
levels of the system architecture of networked sensors. To this end, we develop a post-
SoC/32-bit design point called Hamilton, showing that using integrated components enables
a~ $7 core and shifts hardware modularity to design time. We study the interaction between
hardware and embedded operating systems, identifying that (1) post-SoC motes provide …
The emergence of low-power 32-bit Systems-on-Chip (SoCs), which integrate a 32-bit MCU, radio, and flash, presents an opportunity to re-examine design points and trade-offs at all levels of the system architecture of networked sensors. To this end, we develop a post-SoC/32-bit design point called Hamilton, showing that using integrated components enables a ~$7 core and shifts hardware modularity to design time. We study the interaction between hardware and embedded operating systems, identifying that (1) post-SoC motes provide lower idle current (5.9 μA) than traditional 16-bit motes, (2) 32-bit MCUs are a major energy consumer (e.g., tick increases idle current >50 times), comparable to radios, and (3) thread-based concurrency is viable, requiring only 8.3 μs of context switch time. We design a system architecture, based on a tickless multithreading operating system, with cooperative/adaptive clocking, advanced sensor abstraction, and preemptive packet processing. Its efficient MCU control improves concurrency with ~30% less energy consumption. Together, these developments set the system architecture for networked sensors in a new direction.
ACM Digital Library
以上显示的是最相近的搜索结果。 查看全部搜索结果