A scalable high-current high-accuracy dual-loop four-phase switching LDO for microprocessors

X Mao, Y Lu, RP Martins - IEEE Journal of Solid-State Circuits, 2021 - ieeexplore.ieee.org
High-performance microprocessors need high current (ampere-level), high accuracy, and
fast-response power supplies. Comparing to analog and digital low-dropout (LDO) …

A 1-A Switching LDO With 40-mV Dropout Voltage and Fast DVS

X Mao, Y Lu, RP Martins - … on Circuits and Systems II: Express …, 2023 - ieeexplore.ieee.org
This brief presents a 1-A fully-integrated switching LDO for digital loads. By using 4-phase
200-MHz pulse-width modulation (PWM), it can significantly reduce the output ripple and …

8.7 Dual-use low-drop-out regulator/power gate with linear and on-off conduction modes for microprocessor on-die supply voltages in 14nm

K Luria, J Shor, M Zelikson… - 2015 IEEE International …, 2015 - ieeexplore.ieee.org
In recent generations of microprocessors, there has been an increase in the number and
types of processors integrated on the same die. For example, in [1] several IA (Intel …

A Fully-Digital LDO with Adaptive Clock and Double-Edge-Triggered Shift Register for Quick Response

L Ji, Q Li, X Tong - 2022 7th International Conference on …, 2022 - ieeexplore.ieee.org
This paper presents a digital low-dropout voltage regulator (DLDO) with fast transient
response. When an overshoot or undershoot voltage occurs, a conventional DLDO operates …

A Fully Integrated, Domino-Like-Buffered LDO Regulator With High Power-Supply Rejection Across the Full Frequency Spectrum

JG Lee, HS Kim - IEEE Journal of Solid-State Circuits, 2024 - ieeexplore.ieee.org
This article presents a fully integrated low-dropout (LDO) regulator that offers high power-
supply rejection (PSR) across the full frequency spectrum. The proposed domino-like …

A digital LDO with Co-SA logics and TSPC dynamic latches for fast transient response

L Zhao, Y Lu, RP Martins - IEEE Solid-State Circuits Letters, 2018 - ieeexplore.ieee.org
This letter presents a coarse-line dual-loop digital low-dropout regulator (DLDO), with
combined synchronous and asynchronous logics, designed and measured in a 28-nm bulk …

20.2 digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive voltage scaling multicore processor

WJ Tsou, WH Yang, JH Lin, H Chen… - … Solid-State Circuits …, 2017 - ieeexplore.ieee.org
Multicore processors have been widely used in battery-operated portable systems, desktop,
and server applications, where dynamic voltage scaling (DVS) and adaptive voltage scaling …

A 0.6-V power efficient digital LDO with 99.7% current efficiency utilizing load current aware clock modulation for fast transient response

KG Jayaraman, K Rawy, TT Kim - 2016 IEEE Asia Pacific …, 2016 - ieeexplore.ieee.org
This paper describes a fully integrated, low voltage digital low-dropout voltage (DLDO)
regulator for ultra-low power applications with a load current aware clock modulation …

A residue-current-locked hybrid low-dropout regulator supporting ultralow dropout of sub-50 mV with fast settling time below 10 ns

YH Hwang, J Oh, WS Choi, DK Jeong… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
This article proposes a fully integrated hybrid low-dropout regulator (HLDO) that features an
ultralow dropout and a highly improved transient response. This HLDO incorporates a …

A 270-mA self-calibrating-clocked output-capacitor-free LDO with 0.15–1.15 V output range and 0.183-fs FoM

Y Park, D Jeon - IEEE Transactions on Very Large Scale …, 2022 - ieeexplore.ieee.org
This article proposes a fully integrated output-capacitor-free low-dropout regulator (LDO) for
mobile applications. To overcome the limited output voltage range of typical analog LDOs …