Several circuit architectures have been proposed to overcome logic faults due to the high
defect densities that are expected to be encountered in the first generations of …

This paper presents a defect-tolerant architecture for molecular-based memories. A memory
is designed from multiple modules that share the same address space, where each of the …

The steady downscaling of CMOS technology has led to the development of devices with
nanometer dimensions. Contemporaneously, maturity in technologies such as chemical self …

In this paper, we present a number of parallel and fault-tolerant routing schemes for a set of
nanoscale spin-wave architectures. The architectures considered here have several …

We address the challenge of implementing reliable computation of Boolean functions in
future nanocircuit fabrics. Such fabrics are projected to have very high defect rates. We …

Significant progress has been made in the development of the emerging nanoscale
computing devices. While the ultimate manufacturing process for such devices is uncertain …

This paper will briefly review nanoelectronic challenges while focusing on reliability. We
shall present and analyze a series of CMOS-based examples for addition starting from the …

This paper studies for the first time the performance of von-Neumann multiplexing (vN-MUX)
when stuck at fault model is considered. In this study, vN-MUX is applied to majority (MAJ) …

Predicted device reliability for nanoelectronics indicates that redundant design will be
necessary to build reliable nanosystems. The study of such systems requires the evaluation …

Continued device scaling allows faster and more complex CPUs but comes at the cost of an
increase in the likelihood of CPU failures. This thesis address this worsening problem at the …