Serial addition: Locally connected architectures
V Beiu, S Aunet, J Nyathi, RR Rydberg… - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
This paper will briefly review nanoelectronic challenges while focusing on reliability. We
shall present and analyze a series of CMOS-based examples for addition starting from the …
shall present and analyze a series of CMOS-based examples for addition starting from the …
[PDF][PDF] The vanishing majority gate trading power and speed for reliability
In this paper we are going to explore low-level implementation issues for fault-tolerant
adders based on multiplexing using majority gates (MAJ). We shall analyze the particular …
adders based on multiplexing using majority gates (MAJ). We shall analyze the particular …
On the advantages of serial architectures for low-power reliable computations
V Beiu, S Aunet, J Nyathi, RR Rydberg… - … Processors (ASAP'05 …, 2005 - ieeexplore.ieee.org
This paper explores low power reliable micro-architectures for addition. Power, speed, and
reliability (both defect-and fault-tolerance) are important metrics of system design, spanning …
reliability (both defect-and fault-tolerance) are important metrics of system design, spanning …
An evaluation of asynchronous addition
DJ Kinniment - IEEE Transactions on Very Large Scale …, 1996 - ieeexplore.ieee.org
There is considerable interest at present in the design of asynchronous systems based on
the use of self-timing components for arithmetic and other operations. Amongst the …
the use of self-timing components for arithmetic and other operations. Amongst the …
Area-time-power tradeoffs in parallel adders
C Nagendra, MJ Irwin… - IEEE Transactions on …, 1996 - ieeexplore.ieee.org
In this paper, several classes of parallel, synchronous adders are surveyed based on their
power, delay and area characteristics. The adders studied include the linear time ripple …
power, delay and area characteristics. The adders studied include the linear time ripple …
Low energy asynchronous architectures
I Obridko, R Ginosar - 2005 IEEE International Symposium on …, 2005 - ieeexplore.ieee.org
Asynchronous circuits are often presented as a means of achieving low power operation.
We investigate their suitability for low-energy applications, where long battery life and delay …
We investigate their suitability for low-energy applications, where long battery life and delay …
On computing nano-architectures using unreliable nano-devices
This chapter will start with a brief review of nanoelectronic challenges while focusing on the
reliability challenge. One of the most recent call-to-arms [1] raises two fundamental …
reliability challenge. One of the most recent call-to-arms [1] raises two fundamental …
Threshold voltage variations make full adders reliabilities similar
Addition is the most widely used arithmetic operation in digital applications. The reliability of
full adder (FA) cells is crucial as they affect arithmetic logic and floating-point units, as well …
full adder (FA) cells is crucial as they affect arithmetic logic and floating-point units, as well …
On practical multiplexing issues
V Beiu, MH Sulieman - 2006 Sixth IEEE Conference on …, 2006 - ieeexplore.ieee.org
This paper investigates the behavior of multiplexing schemes in combination with
elementary gates. The two schemes under investigation are MAJORITY-and NAND …
elementary gates. The two schemes under investigation are MAJORITY-and NAND …
Recursive approach to the design of a parallel self-timed adder
MZ Rahman, L Kleeman… - IEEE transactions on very …, 2014 - ieeexplore.ieee.org
This brief presents a parallel single-rail self-timed adder. It is based on a recursive
formulation for performing multibit binary addition. The operation is parallel for those bits that …
formulation for performing multibit binary addition. The operation is parallel for those bits that …