This paper will briefly review nanoelectronic challenges while focusing on reliability. We
shall present and analyze a series of CMOS-based examples for addition starting from the …

In this paper we are going to explore low-level implementation issues for fault-tolerant
adders based on multiplexing using majority gates (MAJ). We shall analyze the particular …

This paper explores low power reliable micro-architectures for addition. Power, speed, and
reliability (both defect-and fault-tolerance) are important metrics of system design, spanning …

There is considerable interest at present in the design of asynchronous systems based on
the use of self-timing components for arithmetic and other operations. Amongst the …

In this paper, several classes of parallel, synchronous adders are surveyed based on their
power, delay and area characteristics. The adders studied include the linear time ripple …

Asynchronous circuits are often presented as a means of achieving low power operation.
We investigate their suitability for low-energy applications, where long battery life and delay …

This chapter will start with a brief review of nanoelectronic challenges while focusing on the
reliability challenge. One of the most recent call-to-arms [1] raises two fundamental …

Addition is the most widely used arithmetic operation in digital applications. The reliability of
full adder (FA) cells is crucial as they affect arithmetic logic and floating-point units, as well …

This paper investigates the behavior of multiplexing schemes in combination with
elementary gates. The two schemes under investigation are MAJORITY-and NAND …

This brief presents a parallel single-rail self-timed adder. It is based on a recursive
formulation for performing multibit binary addition. The operation is parallel for those bits that …