Reliability modeling and evaluation is expected to be one of the major issues in emerging
nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for …

As the sizes of CMOS devices rapidly scale deep into the nanometer range, the manufacture
of nanocircuits will become extremely complex and will inevitably introduce more defects …

A commonly used approach to compute the error rate at the primary outputs (POs) of a circuit
is to compare the fault-free and faulty copies of the circuit using XOR gates. This model …

The low reliability of advanced CMOS devices has become a critical issue that can
potentially supersede the benefits of the technology shrinking process. This is making the …

We propose the probabilistic transfer matrix (PTM) framework to capture nondeterministic
behavior in logic circuits. PTMs provide a concise description of both normal and faulty …

Reliability is fast becoming a major concern due to the nanometric scaling of CMOS
technology. Accurate analytical approaches for the reliability evaluation of logic circuits …

Logic circuits built using nanoscale technologies have significant reliability limitations due to
fundamental physical and manufacturing constraints of their constituent devices. This paper …

The application of current generation computing machines in safety-centric applications like
implantable biomedical chips and automobile safety has immensely increased the need for …

In nano-domain logic circuits, errors generated are transient in nature and will arise due to
the uncertainty or the unreliability of the computing element itself. This type of errors-which …

Well-established reliability models indicate that the failure rates of scaled CMOS will
continue to increase due to manufacturing variability and wear-out caused by negative bias …