Probabilistic maximum error modeling for unreliable logic circuits
K Lingasubramanian, S Bhanja - Proceedings of the 17th ACM Great …, 2007 - dl.acm.org
Reliability modeling and evaluation is expected to be one of the major issues in emerging
nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for …
nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for …
Accurate and efficient estimation of logic circuits reliability bounds
W Ibrahim, M Shousha… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
As the sizes of CMOS devices rapidly scale deep into the nanometer range, the manufacture
of nanocircuits will become extremely complex and will inevitably introduce more defects …
of nanocircuits will become extremely complex and will inevitably introduce more defects …
A Framework for Reliability Analysis of Combinational Circuits Using Approximate Bayesian Inference
S Bathla, V Vasudevan - … on Very Large Scale Integration (VLSI …, 2023 - ieeexplore.ieee.org
A commonly used approach to compute the error rate at the primary outputs (POs) of a circuit
is to compare the fault-free and faulty copies of the circuit using XOR gates. This model …
is to compare the fault-free and faulty copies of the circuit using XOR gates. This model …
Reliability analysis of logic circuits using probabilistic techniques
S Grandhi, C Spagnol… - 2014 10th Conference on …, 2014 - ieeexplore.ieee.org
The low reliability of advanced CMOS devices has become a critical issue that can
potentially supersede the benefits of the technology shrinking process. This is making the …
potentially supersede the benefits of the technology shrinking process. This is making the …
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
S Krishnaswamy, GF Viamontes, IL Markov… - ACM Transactions on …, 2008 - dl.acm.org
We propose the probabilistic transfer matrix (PTM) framework to capture nondeterministic
behavior in logic circuits. PTMs provide a concise description of both normal and faulty …
behavior in logic circuits. PTMs provide a concise description of both normal and faulty …
A stochastic computational approach for accurate and efficient reliability evaluation
Reliability is fast becoming a major concern due to the nanometric scaling of CMOS
technology. Accurate analytical approaches for the reliability evaluation of logic circuits …
technology. Accurate analytical approaches for the reliability evaluation of logic circuits …
Reliability evaluation of logic circuits using probabilistic gate models
Logic circuits built using nanoscale technologies have significant reliability limitations due to
fundamental physical and manufacturing constraints of their constituent devices. This paper …
fundamental physical and manufacturing constraints of their constituent devices. This paper …
Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis
The application of current generation computing machines in safety-centric applications like
implantable biomedical chips and automobile safety has immensely increased the need for …
implantable biomedical chips and automobile safety has immensely increased the need for …
Probabilistic error modeling for nano-domain logic circuits
T Rejimon, K Lingasubramanian… - IEEE Transactions on …, 2008 - ieeexplore.ieee.org
In nano-domain logic circuits, errors generated are transient in nature and will arise due to
the uncertainty or the unreliability of the computing element itself. This type of errors-which …
the uncertainty or the unreliability of the computing element itself. This type of errors-which …
[PDF][PDF] Device variability impact on logic gate failure rates
E Taylor, J Fortes - Proceedings of the 16th IEEE Int. Conf. Application …, 2005 - Citeseer
Well-established reliability models indicate that the failure rates of scaled CMOS will
continue to increase due to manufacturing variability and wear-out caused by negative bias …
continue to increase due to manufacturing variability and wear-out caused by negative bias …