In this paper we present the first detailed analysis of von Neumann multiplexing (vN-MUX)
using majority (MAJ) gates of small fan-ins Δ (MAJ-Δ) with respect to the probability of failure …

This paper presents an exact reliability analysis of von Neumann multiplexing using majority
gates of fan-in Δ= 3, 5, 7, 9, 11, and the corresponding minimum redundancy factors R= 6 …

Motivated by the need for cost-effective fault-tolerant nano architectures, we explore von
Neumann multiplexing (vN-MUX) at small and very small redundancy factors. We present a …

This paper starts by reviewing many of the gate-level reliability analyses of von Neumann
multiplexing (vN-MUX). It goes on to detail very accurate device-level (CMOS technology …

The nanometer scale of device manufacturing in the semiconductor industry is characterized
by two features (i) high defect rate at the substrate, and (ii) availability of large number of …

This paper investigates the behavior of multiplexing (MUX) schemes in combination with the
elementary gates. The two schemes under investigation are majority (MAJ) and NAND MUX …

Motivated by the need for economical fault-tolerant designs for nanoarchitectures, we
explore a novel multiplexing-based redundant design scheme at small (/spl les/100) and …

This paper investigates the behavior of multiplexing schemes in combination with
elementary gates. The two schemes under investigation are MAJORITY-and NAND …

Nanoelectronic systems are anticipated to be highly susceptible to computation and
communication noise. Interestingly, von Neumann addressed the issue of computation in the …

As conventional silicon CMOS technology continues to shrink, logic circuits are increasingly
subject to errors induced by electrical noise. In addition, device reliability will become a …