Progress in autonomous fault recovery of field programmable gate arrays
MG Parris, CA Sharma, RF Demara - ACM Computing Surveys (CSUR), 2011 - dl.acm.org
The capabilities of current fault-handling techniques for Field Programmable Gate Arrays
(FPGAs) develop a descriptive classification ranging from simple passive techniques to …
(FPGAs) develop a descriptive classification ranging from simple passive techniques to …
[图书][B] Managing temperature effects in nanoscale adaptive systems
This book discusses new techniques for detecting, controlling, and exploiting the impacts of
temperature variations on nanoscale circuits and systems. A new sensor system is …
temperature variations on nanoscale circuits and systems. A new sensor system is …
Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications
M Abramovici, C Strond, C Hamilton… - … (IEEE Cat. No …, 1999 - ieeexplore.ieee.org
In this paper we present a novel integrated approach to on-line FPGA testing, diagnosis, and
fault-tolerance, to be used in high-reliability and high-availability hardware. The test process …
fault-tolerance, to be used in high-reliability and high-availability hardware. The test process …
BIST-based test and diagnosis of FPGA logic blocks
M Abramovici, CE Stroud - IEEE Transactions on Very Large …, 2001 - ieeexplore.ieee.org
We present a built-in self-test (BIST) approach able to detect and accurately diagnose all
single and practically all multiple faulty programmable logic blocks (PLBs) in field …
single and practically all multiple faulty programmable logic blocks (PLBs) in field …
A survey of fault tolerant methodologies for FPGAs
JA Cheatham, JM Emmert, S Baumgart - ACM Transactions on Design …, 2006 - dl.acm.org
A wide range of fault tolerance methods for FPGAs have been proposed. Approaches range
from simple architectural redundancy to fully on-line adaptive implementations. The …
from simple architectural redundancy to fully on-line adaptive implementations. The …
Dynamic fault tolerance in FPGAs via partial reconfiguration
J Emmert, C Stroud, B Skaggs… - Proceedings 2000 IEEE …, 2000 - ieeexplore.ieee.org
In this paper we present an on-line, multi-level fault tolerant (FT) technique for system
functions and applications mapped to partially and dynamically reconfigurable FPGAs. Our …
functions and applications mapped to partially and dynamically reconfigurable FPGAs. Our …
Online fault tolerance for FPGA logic blocks
JM Emmert, CE Stroud… - IEEE Transactions on Very …, 2007 - ieeexplore.ieee.org
Most adaptive computing systems use reconfigurable hardware in the form of field
programmable gate arrays (FPGAs). For these systems to be fielded in harsh environments …
programmable gate arrays (FPGAs). For these systems to be fielded in harsh environments …
Design of a novel fault-tolerant voter circuit for TMR implementation to improve reliability in digital circuits
RV Kshirsagar, RM Patrikar - Microelectronics Reliability, 2009 - Elsevier
Due to the shrinking of feature size and significant reduction in noise margins, nanoscale
circuits have become more susceptible to manufacturing defects, interference from radiation …
circuits have become more susceptible to manufacturing defects, interference from radiation …
Self-adaptive system for addressing permanent errors in on-chip interconnects
We present a self-contained adaptive system for detecting and bypassing permanent errors
in on-chip interconnects. The proposed system reroutes data on erroneous links to a set of …
in on-chip interconnects. The proposed system reroutes data on erroneous links to a set of …
Column-based precompiled configuration techniques for FPGA
WJ Huang, EJ McCluskey - The 9th Annual IEEE Symposium …, 2001 - ieeexplore.ieee.org
The abundance of configurable logic elements and routing resources in recent Field-
Programmable Gate Arrays (FPGAs) provides a cost-effective method for tolerating …
Programmable Gate Arrays (FPGAs) provides a cost-effective method for tolerating …