Warpage Estimation and Demonstration of Panel-Level Fan-Out Packaging With Cu Pillars Applied on a Highly Integrated Architecture

CC Lee, CP Chang, CY Chen, HC Lee… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Fan-out panel-level packaging (FO-PLP) has become a critical forward-looking technology
because it can meet the demands for small size, high input–output counts, and multichip …

State-of-the-art of advanced packaging

JH Lau - Chiplet Design and Heterogeneous Integration …, 2023 - Springer
In this chapter, advanced packaging is defined. The kinds of advanced packaging are
ranked based on their interconnect density and electrical performance, and are grouped into …

[HTML][HTML] Delamination of Plasticized Devices in Dynamic Service Environments

W Tian, X Chen, G Zhang, Y Chen, J Luo - Micromachines, 2024 - mdpi.com
With the continuous development of advanced packaging technology in heterogeneous
semiconductor integration, the delamination failure problem in a dynamic service …

A low-loss fan-out wafer-level package with a novel redistribution layer pattern and its measurement methodology for millimeter-wave application

H Dong, J Chen, D Hou, Y Xiang… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
A low-loss fan-out wafer-level package (FOWLP) has been proposed for millimeter-wave
application. To ensure the radio frequency (RF) signal transition in a ground-signal-ground …

Holistic Chiplet–Package Co-Optimization for Agile Custom 2.5-D Design

MDA Kabir, Y Peng - IEEE Transactions on Components …, 2021 - ieeexplore.ieee.org
With the increasing popularity and applications of 2.5-D integration, both chip and
packaging industries are making significant progress in this direction. In advanced high …

Engineering applications and technical challenges of active array microsystems

J Lu, H Zhu - Frontiers of Information Technology & Electronic …, 2024 - Springer
In the post-Moore era, the development of active phased array antennas will inevitably trend
towards active array microsystems. In this paper, the characteristics and composition of the …

Research on Surface Morphology of Gold Micro Bumps Based on Monte Carlo Method

H Ji, W Tian, H Qian, X Sun, Y Wang, L Gu, L Zheng - Micromachines, 2023 - mdpi.com
In advanced packaging technology, the micro bump has become an important means of chip
stacking and wafer interconnection. The reliability of micro bumps, which plays an important …

Comparative study of solder joint reliability assessment on fan-out CSP and flip-chip DCA package

V Liu, K Sinha, CT Chen, YJ Chen, YY Chen… - Journal of Materials …, 2023 - Springer
The increasing demand over the higher density and smaller form factor of memory packages
have become a mainstream due to the boom of artificial intelligence and 5G/6G. While form …

Synthesis and Characterization of Negative-Tone Photosensitive Polyimides with Low Coefficient of Thermal Expansion for Packaging Applications

P Zhang, H Wang, P Xia, X Chen, W Zhao, C Wang… - Polymers, 2024 - mdpi.com
Negative-tone photosensitive polyimides (PSPIs) with a low coefficient of thermal expansion
(CTE) were prepared by dissolving polyimide precursor-poly (amide ester)(PAE) resins …

Prediction and Analysis of Radiated EMI From a Wafer-Level Package Based on IC Source Modeling

JH Cho, S Jeong, JB Kim, JD Ihm… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
This article proposes a comprehensive analysis and prediction method for wafer-level
radiated electromagnetic interference (EMI) based on integrated circuit (IC) source …