A memory device includes a memory array comprising a plurality of memory cells, a plurality
of sense amplifiers configured to sense data stored in the memory cells of the memory array …

Portable digital systems need to be not just low power but power efficient as they are
powered by low batteries or energy harvesters. Energy harvesting systems tend to provide …

OpenRAM is an open-source framework for the development of memories with an initial
focus on SRAMs. OpenRAM provides an application interface for netlist, layout, and …

High performance systems often employ multi-ported memories to enhance the throughput
and flexibility of the memory. Existing SRAM compilers offer limited control over the SRAM …

This paper proposes schemes for the direct measurement of bit-line (BL) voltage swing,
sense amplifier (SA) offset voltage, and word-line (WL) pulse width, demonstrated in a 40 …

A new dynamic cache resizing scheme for low-power CAM-tag caches is introduced. A
control algorithm that is only activated on cache misses uses a duplicate set of tags, the miss …

The paper presents SRAM cache design in 5nm FinFET technology for L2/L3 cache
applications, demonstrating circuit techniques to enable wide-range DVFS (Dynamic …

(57) ABSTRACT A memory has an array of memory cells, a word line driver, a sense
amplifier, and a sense enable circuit. Each memory cell has a coupling transistor for …

Computing-in-Memory is an emerging paradigm that promises to accelerate data-intensive
computation by eliminating the back and forth data movement between the memory and …

The access timing control of low-voltage static random access memory cells encounters
crucial challenges in the presence of within-die (WID) variations, which induce severe delay …