A long bitline precharge time in the write operation and a wide wordline pulse width in the
read operation dominate the cycle time of large-capacity compilable SRAMs. A data …

Two 8kbit SRAMs, one using a replica technique and the other using an inverter chain delay
as timing control for word line and sense amplifiers, are simulated in 90nm CMOS …

Energetic particle (alpha particle, cosmic neutron, etc.) induced single event data upset or
soft error has emerged as a key reliability concern in SRAMs in sub-100 nanometre …

With the development of modern semiconductor fabrication technology, the channel length
of the CMOS device and the device pitch continually shrink accompanied by more and more …

To mitigate the single-event effect, improve the stability and also maintain the low power
characteristic of sub-threshold SRAM, a Dual Interlocked Storage Cell (DICE) based SRAM …

Timing variation of sense amplifier enable (SAE) attributable to the random variation of
transistor threshold Voltage is reduced by a novel Multi Replica Bitline Delay technique to …

Crosstalk between bitlines induces read failure and limits the coverage of applicable code-
patterns for high-speed contact/via-programming read-only memories (ROMs) in SoC …

Broadly, the present invention provides a duplicate col umn of bit cells, a predetermined
number of which are set to a predetermined State and coupled together So that they are all …

(57) ABSTRACT A Semiconductor memory circuit including a plurality of bit lines, memory
cells connected to each of Said plurality of bit lines, Sense amplifiers, each corresponding to …

As process technology continues to scale, SRAM test quality has become a growing concern
in modern System-on-Chips. Ensuring high test quality while keeping costs low requires …