Survey of microarchitectural side and covert channels, attacks, and defenses

J Szefer - Journal of Hardware and Systems Security, 2019 - Springer
Over the last two decades, side and covert channel research has shown a variety of ways of
exfiltrating information for a computer system. Processor microarchitectural timing-based …

LVI: Hijacking transient execution through microarchitectural load value injection

J Van Bulck, D Moghimi, M Schwarz… - … IEEE Symposium on …, 2020 - ieeexplore.ieee.org
The recent Spectre attack first showed how to inject incorrect branch targets into a victim
domain by poisoning microarchitectural branch prediction history. In this paper, we …

Inferring fine-grained control flow inside {SGX} enclaves with branch shadowing

S Lee, MW Shih, P Gera, T Kim, H Kim… - 26th USENIX Security …, 2017 - usenix.org
Intel has introduced a hardware-based trusted execution environment, Intel Software Guard
Extensions (SGX), that provides a secure, isolated execution environment, or enclave, for a …

Last-level cache side-channel attacks are practical

F Liu, Y Yarom, Q Ge, G Heiser… - 2015 IEEE symposium on …, 2015 - ieeexplore.ieee.org
We present an effective implementation of the Prime+ Probe side-channel attack against the
last-level cache. We measure the capacity of the covert channel the attack creates and …

Branchscope: A new side-channel attack on directional branch predictor

D Evtyushkin, R Riley, NCSEECE Abu-Ghazaleh… - ACM SIGPLAN …, 2018 - dl.acm.org
We present BranchScope-a new side-channel attack where the attacker infers the direction
of an arbitrary conditional branch instruction in a victim program by manipulating the shared …

A survey of timing channels and countermeasures

AK Biswas, D Ghosal, S Nagaraja - ACM Computing Surveys (CSUR), 2017 - dl.acm.org
A timing channel is a communication channel that can transfer information to a
receiver/decoder by modulating the timing behavior of an entity. Examples of this entity …

A survey of microarchitectural timing attacks and countermeasures on contemporary hardware

Q Ge, Y Yarom, D Cock, G Heiser - Journal of Cryptographic Engineering, 2018 - Springer
Microarchitectural timing channels expose hidden hardware states though timing. We survey
recent attacks that exploit microarchitectural features in shared hardware, especially as they …

{FLUSH+ RELOAD}: A high resolution, low noise, l3 cache {Side-Channel} attack

Y Yarom, K Falkner - 23rd USENIX security symposium (USENIX security …, 2014 - usenix.org
Sharing memory pages between non-trusting processes is a common method of reducing
the memory footprint of multi-tenanted systems. In this paper we demonstrate that, due to a …

Cachezoom: How SGX amplifies the power of cache attacks

A Moghimi, G Irazoqui, T Eisenbarth - Cryptographic Hardware and …, 2017 - Springer
In modern computing environments, hardware resources are commonly shared, and parallel
computation is widely used. Parallel tasks can cause privacy and security problems if proper …

Lord of the ring (s): Side channel attacks on the {CPU}{On-Chip} ring interconnect are practical

R Paccagnella, L Luo, CW Fletcher - 30th USENIX Security Symposium …, 2021 - usenix.org
We introduce the first microarchitectural side channel attacks that leverage contention on the
CPU ring interconnect. There are two challenges that make it uniquely difficult to exploit this …