Modeling SRAM start-up behavior for physical unclonable functions

M Cortez, A Dargar, S Hamdioui… - 2012 IEEE International …, 2012 - ieeexplore.ieee.org
One of the emerging technologies for cryptographic key storage is hardware intrinsic
security based on Physical Unclonable Functions (PUFs); a PUF is a physical structure of a …

Analysis of SRAM metrics for data dependent BTI degradation and process variability

JB Shaik, S Singhal, N Goel - Integration, 2020 - Elsevier
Abstract Bias Temperature Instability (BTI) is one of the most crucial reliability issues in
modern CMOS technology. It leads to shift in device parameters, which eventually affect …

RRAM-based non-volatile SRAM cell architectures for ultra-low-power applications

H Bazzi, A Harb, H Aziza, M Moreau… - Analog Integrated Circuits …, 2021 - Springer
Abstract Static Random-Access Memories (SRAMs) have flourished in the memory market
relying on their speed, power consumption and compatibility with standard CMOS process …

A novel sort error hardened 10T SRAM cells for low voltage operation

IS Jung, YB Kim, F Lombardi - 2012 IEEE 55th International …, 2012 - ieeexplore.ieee.org
In this paper, two types of a soft error hardened 10T SRAM cells with high static noise
margin (SNM) are proposed for low voltage operation. The proposed NMOS stacked SRAM …

10T SRAM Using Half- Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage

N Maroof, BS Kong - IEEE transactions on very large scale …, 2016 - ieeexplore.ieee.org
We present, in this paper, a new 10T static random access memory cell having single ended
decoupled read-bitline (RBL) with a 4T read port for low power operation and leakage …

An SRAM-based multibit in-memory matrix-vector multiplier with a precision that scales linearly in area, time, and power

R Khaddam-Aljameh, PA Francese… - … Transactions on Very …, 2020 - ieeexplore.ieee.org
A novel interleaved switched-capacitor and SRAM-based multibit matrix-vector multiply-
accumulate engine for in-memory computing is presented. Its operation principle is based …

[图书][B] Variation-aware advanced CMOS devices and SRAM

C Shin - 2016 - Springer
There is no doubt that advanced silicon integrated circuit (IC) technology has thoroughly
changed the way we live. Human life has become much more convenient since hand-held …

Design of a hybrid memory cell using memristance and ambipolarity

P Junsangsri, F Lombardi - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
This paper presents a novel circuit of a memory cell consisting of a memristor and ambipolar
transistors. Macroscopic models are utilized to characterize the nonvolatile feature of the …

[PDF][PDF] Static noise margin analysis of SRAM cell for high speed application

D Mukherjee, HK Mondal, BVR Reddy - International Journal of Computer …, 2010 - Citeseer
This paper presents the different types of analysis such as noise, voltage, read margin and
write margin of Static Random Access Memory (SRAM) cell for high-speed application. The …

A Comparative Study of 6T, 8T and 9T Decanano SRAM cell

P Athe, S Dasgupta - 2009 IEEE Symposium on Industrial …, 2009 - ieeexplore.ieee.org
Data retention and leakage current reduction are among the major area of concern in
today's CMOS technology. In this paper 6T, 8T and 9T SRAM cell have been compared on …