A survey on FFT/IFFT processors for next generation telecommunication systems
E Konguvel, M Kannan - Journal of Circuits, Systems and …, 2018 - World Scientific
The Fast Fourier Transform and Inverse Fast Fourier Transform (FFT/IFFT) are the most
significant digital signal processing (DSP) techniques used in Orthogonal Frequency …
significant digital signal processing (DSP) techniques used in Orthogonal Frequency …
VLSI design and implementation of reconfigurable 46-mode combined-radix-based FFT hardware architecture for 3GPP-LTE applications
XY Shih, HR Chou, YQ Liu - … on Circuits and Systems I: Regular …, 2017 - ieeexplore.ieee.org
This paper presents a reconfigurable fast Fourier transform (FFT) hardware architecture,
supporting 46 different FFT sizes defined in 3GPP-LTE applications. Our proposed design …
supporting 46 different FFT sizes defined in 3GPP-LTE applications. Our proposed design …
An area efficient vedic multiplier for FFT processor implementation using 4-2 compressor adder
S Dhanasekar - International Journal of Electronics, 2024 - Taylor & Francis
This article proposes a compact compressor adder of Vedic multiplication for an area-
efficient FFT architecture. A standard multi-radix-24, 22, 23 FFT with a single-path delay …
efficient FFT architecture. A standard multi-radix-24, 22, 23 FFT with a single-path delay …
PAPR reduction of OFDM systems using H‐SLM method with a multiplierless IFFT/FFT technique
NA Sivadas - ETRI Journal, 2022 - Wiley Online Library
This study proposes a novel low‐complexity algorithm for computing inverse fast Fourier
transform (IFFT)/fast Fourier transform (FFT) operations in binary phase shift keying …
transform (IFFT)/fast Fourier transform (FFT) operations in binary phase shift keying …
An area effective OFDM transceiver system with multi-radix FFT/IFFT algorithm for wireless applications
An area effective Orthogonal Frequency Division Multiplexing (OFDM) transceiver design
with Multi-radix FFT/IFFT algorithm is introduced for wireless applications. The Pseudo …
with Multi-radix FFT/IFFT algorithm is introduced for wireless applications. The Pseudo …
Design and implementation of high speed, low complexity FFT/IFFT processor using modified mixed radix-24–22-23 algorithm for high data rate applications
CA Arun, M Sahayasheela, G Gnanaguru - International Journal of …, 2023 - Springer
A modified mixed radix algorithm with low complexity based Fast Fourier Transform (FFT)
processor for large data rate applications is presented in this paper. In order to reduce the …
processor for large data rate applications is presented in this paper. In order to reduce the …
Efficient FPGA implementation of high-throughput mixed radix multipath delay commutator FFT processor for MIMO-OFDM
M Dali, A Guessoum, RM Gibson… - … in Electrical and …, 2017 - researchonline.gcu.ac.uk
This article presents and evaluates pipelined architecture designs for an improved high-
frequency Fast Fourier Transform (FFT) processor implemented on Field Programmable …
frequency Fast Fourier Transform (FFT) processor implemented on Field Programmable …
[PDF][PDF] VLSI implementation of variable bit rate OFDM transceiver system with multi-radix FFT/IFFT processor for wireless applications
D SUBRAMANIYAM, R JAYABALAN - Journal of Electrical …, 2018 - academia.edu
In this paper, a Variable Bit Rate 64 Subcarrier OFDM Transceiver system is implemented in
FPGA and the Modified Multi-radix 64 point FFT/IFFT blocks present in the OFDM design is …
FPGA and the Modified Multi-radix 64 point FFT/IFFT blocks present in the OFDM design is …
Area-efficient scheduling scheme based FFT processor for various OFDM systems
JK Jang, HK Kim, MH Sunwoo… - 2018 IEEE Asia Pacific …, 2018 - ieeexplore.ieee.org
This paper presents an area-efficient fast Fourier transform (FFT) processor for orthogonal
frequency-division multiplexing systems based on multi-path delay commutator architecture …
frequency-division multiplexing systems based on multi-path delay commutator architecture …
A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition
X Wei, H Yang, W Li, Z Huang, T Yin, L Yu - Integration, 2019 - Elsevier
This paper presents a high throughput size-configurable floating point (FP) Fast Fourier
Transform (FFT) processor, having implemented the 8-parallel multi-path delay feedback …
Transform (FFT) processor, having implemented the 8-parallel multi-path delay feedback …