FPGA device and method that includes a variable grain function architecture for implementing configuration logic blocks and a complimentary variable length …

OP Agrawal, HM Chang, BA Sharpe-Geisler… - US Patent …, 2001 - Google Patents
A field-programmable gate array device (FPGA) having plural rows and columns of logic
function units is organized with symmetrical and complementary Variable Grain Architecture …

Node-covering based defect and fault tolerance methods for increased yield in FPGAs

F Hanchek, S Dutt - … of 9th International Conference on VLSI …, 1996 - ieeexplore.ieee.org
Fault tolerant techniques are proposed which make use of the reconfigurability of SRAM-
based field programmable gate arrays (FPGAs). Based on the principle of node-covering, a …

Architectural and physical design challenges for one-million gate FPGAs and beyond

J Rose, D Hill - Proceedings of the 1997 ACM fifth international …, 1997 - dl.acm.org
Process technology advances tell us that the one-million gate Field-Programmable Gate
Array (FPGA) will soon be here, and larger devices shortly after that. We feel that current …

Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement

JM Emmert, D Bhatia - … Workshop on Field Programmable Logic and …, 1997 - Springer
Field-programmable gate arrays have the potential to provide reconfigurability in the
presence of faults. In this paper, we have investigated the problem of partially reconfiguring …

On-line fault tolerant operation via incremental reconfiguration of field programmable gate arrays

M Abramovici, CE Stroud, JM Emmert - US Patent 6,530,049, 2003 - Google Patents
A method of fault tolerant operation of field programmable gate arrays (FPGAs) utilizing
incremental reconfiguration during normal on-line operation includes configuring an FPGA …

Yield enhancement of reconfigurable microfluidics-based biochips using interstitial redundancy

F Su, K Chakrabarty - ACM Journal on Emerging Technologies in …, 2006 - dl.acm.org
Microfluidics-based biochips for biochemical analysis are currently receiving much attention.
They automate highly repetitive laboratory procedures by replacing cumbersome equipment …

A high-speed asynchronous decompression circuit for embedded processors

M Benes, A Wolfe, SM Nowick - … Seventeenth Conference on …, 1997 - ieeexplore.ieee.org
This paper describes the architecture and implementation of a high-speed decompression
engine for embedded processors. The engine is targeted to processors where embedded …

Defect tolerance for gracefully-degradable microfluidics-based biochips

F Su, K Chakrabarty - 23rd IEEE VLSI Test Symposium (VTS'05 …, 2005 - ieeexplore.ieee.org
Defect tolerance is an important design consideration for microfluidics-based biochips that
are used for safety-critical applications. We propose a defect tolerance methodology based …

A survey on fault tolerance in FPGAs

B Harikrishna, S Ravi - 2013 7th International Conference on …, 2013 - ieeexplore.ieee.org
An FPGA (Field Programmable Gate Array) is a device that contains a matrix of
reconfigurable gate array logic circuitry. During FPGA configuration, the internal circuitry is …

A novel printed-lookup-table-based programmable printed digital circuit

AT Erozan, DD Weller, F Rasheed… - … Transactions on Very …, 2020 - ieeexplore.ieee.org
Advances in printed electronics (PE) enables new applications, particularly in ultra-low-cost
domains. However, achieving high-throughput printing processes and manufacturing yield is …