A survey of hardware self-organizing maps

S Jovanović, H Hikawa - IEEE Transactions on Neural …, 2022 - ieeexplore.ieee.org
Self-organizing feature maps (SOMs) are commonly used technique for clustering and data
dimensionality reduction in many application fields. Indeed, their inherent property of …

Improved learning performance of hardware self-organizing map using a novel neighborhood function

H Hikawa, Y Maeda - … on neural networks and learning systems, 2015 - ieeexplore.ieee.org
Many self-organizing maps (SOMs) implemented on hardware restrict their neighborhood
function values to negative powers of two. In this paper, we propose a novel hardware …

A reconfigurable neuroprocessor for self-organizing feature maps

J Lachmair, E Merenyi, M Porrmann, U Rückert - Neurocomputing, 2013 - Elsevier
In this paper we compare a scalable FPGA-based hardware accelerator for the emulation of
Self-Organizing Feature Maps (SOMs) with a multi-threaded software implementation on a …

Nested hardware architecture for self-organizing map

H Hikawa - 2019 International Joint Conference on Neural …, 2019 - ieeexplore.ieee.org
This paper proposes a hardware SOM architecture with nested structure. The proposed
hardware SOM is made of a single module, and the module is made of four smaller …

Hardware-in-the-loop simulations for FPGA-based digital control design

C Paiz, C Pohl, M Porrmann - … and Robotics: Selected Papers from the …, 2008 - Springer
A framework to perform hardware-in-the-loop (HIL) simulations in the designflow of digital
controllers, based on Field Programmable Gate Array (FPGA) technology, is presented. The …

[图书][B] Run-time reconfigurable multiprocessors

M Purnaprajna - 2010 - researchgate.net
The advantage in multiprocessors is the performance speedup obtained with processorlevel
parallelism. Similarly, the flexibility for application-specific adaptability is the advantage in …

A new hardware self-organizing map architecture with high expandability

H Hikawa, H Ito, Y Maeda - 2018 IEEE International …, 2018 - ieeexplore.ieee.org
This paper proposes a new scalable hardware SOM architecture in which neurons can
easily be increased. Learning of SOM is made of two operations, ie, winner search and …

Design of low-power gesture recognition system and self-organizing map processors

Y Lu - 2023 - dr.ntu.edu.sg
Machine learning applications have gained substantial recognition in recent years due to
their significant impact on a myriad of sectors such as healthcare, automation, and artificial …

Exploring liquid computing in a hardware adaptation: construction and operation of a neural network experiment

F Schürmann - 2005 - archiv.ub.uni-heidelberg.de
Future increases in computing power strongly rely on miniaturization, large scale integration,
and parallelization. Yet, approaching the nanometer realm poses new challenges in terms of …

[PDF][PDF] Hardware accelerated real time classification of hyperspectral imaging data for coffee sorting.

A Backhaus, J Lachmair, U Rückert, U Seiffert - ESANN, 2012 - Citeseer
Hyperspectral imaging has been proven to be a viable tool for automated food inspection
that is non-invasive and on-line capable. In this contribution a hardware implemented Self …