A survey on FFT/IFFT processors for next generation telecommunication systems
E Konguvel, M Kannan - Journal of Circuits, Systems and …, 2018 - World Scientific
The Fast Fourier Transform and Inverse Fast Fourier Transform (FFT/IFFT) are the most
significant digital signal processing (DSP) techniques used in Orthogonal Frequency …
significant digital signal processing (DSP) techniques used in Orthogonal Frequency …
A combined SDC-SDF architecture for normal I/O pipelined radix-2 FFT
We present an efficient combined single-path delay commutator-feedback (SDC-SDF) radix-
2 pipelined fast Fourier transform architecture, which includes log 2 N-1 SDC stages, and 1 …
2 pipelined fast Fourier transform architecture, which includes log 2 N-1 SDC stages, and 1 …
A Mixed-Decimation MDF Architecture for Radix- Parallel FFT
J Wang, C Xiong, K Zhang, J Wei - IEEE transactions on very …, 2015 - ieeexplore.ieee.org
This paper presents a mixed-decimation multipath delay feedback (M2 DF) approach for the
radix-2 k fast Fourier transform. We employ the principle of folding transformation to derive …
radix-2 k fast Fourier transform. We employ the principle of folding transformation to derive …
An area efficient vedic multiplier for FFT processor implementation using 4-2 compressor adder
S Dhanasekar - International Journal of Electronics, 2024 - Taylor & Francis
This article proposes a compact compressor adder of Vedic multiplication for an area-
efficient FFT architecture. A standard multi-radix-24, 22, 23 FFT with a single-path delay …
efficient FFT architecture. A standard multi-radix-24, 22, 23 FFT with a single-path delay …
A variable-size FFT hardware accelerator based on matrix transposition
X Chen, Y Lei, Z Lu, S Chen - IEEE Transactions on Very Large …, 2018 - ieeexplore.ieee.org
Fast Fourier transform (FFT) is the kernel and the most time-consuming algorithm in the
domain of digital signal processing, and the FFT sizes of different applications are very …
domain of digital signal processing, and the FFT sizes of different applications are very …
Challenging the limits of FFT performance on FPGAs
M Garrido, M Acevedo, A Ehliar… - … on Integrated Circuits …, 2014 - ieeexplore.ieee.org
This paper analyzes the limits of FFT performance on FPGAs. For this purpose, a FFT
generation tool has been developed. This tool is highly parameterizable and allows for …
generation tool has been developed. This tool is highly parameterizable and allows for …
Multiplierless unity-gain SDF FFTs
In this brief, we propose a novel approach to implement multiplierless unity-gain single-
delay feedback fast Fourier transforms (FFTs). Previous methods achieve unity-gain FFTs by …
delay feedback fast Fourier transforms (FFTs). Previous methods achieve unity-gain FFTs by …
VLSI implementation of an area and energy efficient FFT/IFFT core for MIMO-OFDM applications
K Elango, K Muniandi - Annals of Telecommunications, 2020 - Springer
This research article presents an implementation of high-performance Fast Fourier
Transform (FFT) and Inverse Fast Fourier Transform (IFFT) core for multiple input multiple …
Transform (FFT) and Inverse Fast Fourier Transform (IFFT) core for multiple input multiple …
A pipelined area-efficient and high-speed reconfigurable processor for floating-point FFT/IFFT and DCT/IDCT computations
M Wang, F Wang, S Wei, Z Li - Microelectronics Journal, 2016 - Elsevier
For scientific computing and high-resolution imaging applications, this paper presents a
pipelined reconfigurable processor to implement variable-length single-precision floating …
pipelined reconfigurable processor to implement variable-length single-precision floating …
Design and implementation of high speed, low complexity FFT/IFFT processor using modified mixed radix-24–22-23 algorithm for high data rate applications
CA Arun, M Sahayasheela, G Gnanaguru - International Journal of …, 2023 - Springer
A modified mixed radix algorithm with low complexity based Fast Fourier Transform (FFT)
processor for large data rate applications is presented in this paper. In order to reduce the …
processor for large data rate applications is presented in this paper. In order to reduce the …