SRAM cell design challenges in modern deep sub-micron technologies: An overview

W Gul, M Shams, D Al-Khalili - Micromachines, 2022 - mdpi.com
Microprocessors use static random-access memory (SRAM) cells in the cache memory
design. As a part of the central computing component, their performance is critical. Modern …

Leakage current: Moore's law meets static power

NS Kim, T Austin, D Baauw, T Mudge, K Flautner… - …, 2003 - ieeexplore.ieee.org
Off-state leakage is static power, current that leaks through transistors even when they are
turned off. The other source of power dissipation in today's microprocessors, dynamic power …

[图书][B] Computer architecture techniques for power-efficiency

S Kaxiras, M Martonosi - 2008 - books.google.com
In the last few years, power dissipation has become an important design constraint, on par
with performance, in the design of new computer systems. Whereas in the past, the primary …

Survey of energy-cognizant scheduling techniques

S Zhuravlev, JC Saez, S Blagodurov… - … on Parallel and …, 2012 - ieeexplore.ieee.org
Execution time is no longer the only metric by which computational systems are judged. In
fact, explicitly sacrificing raw performance in exchange for energy savings is becoming a …

[图书][B] Robust SRAM designs and analysis

J Singh, SP Mohanty, DK Pradhan - 2012 - books.google.com
This book provides a guide to Static Random Access Memory (SRAM) bitcell design and
analysis to meet the nano-regime challenges for CMOS devices and emerging devices …

Low-power cache design using 7T SRAM cell

RE Aly, MA Bayoumi - … Transactions on Circuits and Systems II …, 2007 - ieeexplore.ieee.org
On-chip cache consumes a large percentage of the whole chip area and expected to
increase in advanced technologies. Charging/discharging large bit lines capacitance …

Circuit and microarchitectural techniques for reducing cache leakage power

NS Kim, K Flautner, D Blaauw… - IEEE Transactions on …, 2004 - ieeexplore.ieee.org
On-chip caches represent a sizable fraction of the total power consumption of
microprocessors. As feature sizes shrink, the dominant component of this power …

Sleepy stack leakage reduction

JC Park, VJ Mooney III - IEEE transactions on very large scale …, 2006 - ieeexplore.ieee.org
Leakage power consumption of current CMOS technology is already a great challenge.
International Technology Roadmap for Semiconductors projects that leakage power …

Leakage power analysis of a 90nm FPGA

T Tuan, B Lai - Proceedings of the IEEE 2003 Custom …, 2003 - ieeexplore.ieee.org
Reconfigurable architectures, including FPGAs, are promising solutions for managing
increasing design complexity while achieving both performance and flexibility. To support …

[图书][B] Low-power electronics design

C Piguet - 2018 - books.google.com
The power consumption of integrated circuits is one of the most problematic considerations
affecting the design of high-performance chips and portable devices. The study of power …