Secure and optimized load balancing for multitier IoT and edge-cloud computing systems

WZ Zhang, IA Elgendy, M Hammad… - IEEE Internet of …, 2020 - ieeexplore.ieee.org
Mobile-edge computing (MEC) has emerged as a new computing paradigm with great
potential to alleviate resource limitations attributed to mobile device users (MDUs) by …

[HTML][HTML] A low area high speed FPGA implementation of AES architecture for cryptography application

TM Kumar, KS Reddy, S Rinaldi, BD Parameshachari… - Electronics, 2021 - mdpi.com
Nowadays, a huge amount of digital data is frequently changed among different embedded
devices over wireless communication technologies. Data security is considered an important …

A review on fpga implementation of lightweight cryptography for wireless sensor network

B Sreehari, V Sankar, RS Lopez… - 2023 International …, 2023 - ieeexplore.ieee.org
Wireless sensor networks (WSNs) have become increasingly popular in recent years due to
their ability to remotely monitor and gather data in a variety of applications. The frequent …

Energy-efficient and security-aware task offloading for multi-tier edge-cloud computing systems

W Almuseelem - IEEE Access, 2023 - ieeexplore.ieee.org
Recently, edge-cloud computing (ECC) has emerged as a new paradigm for alleviating the
intensive overhead for mobile IoT applications. However, data security remains a significant …

A secure data parallel processing based embedded system for internet of things computer vision using field programmable gate array devices

KN Qureshi, S Qayyum, MN Ul Islam… - International Journal of …, 2021 - Wiley Online Library
Technologies and new standards have converted the traditional networks and systems into
new smart cities integrated networks. Different factors are behind to build these new …

Design and implementation of power and area optimized AES architecture on FPGA for IoT application

P Rajasekar, H Mangalam - Circuit World, 2020 - emerald.com
Purpose The growing trends in the usage of hand held devices necessitate the need to
design them with low power consumption and less area design. Besides, information …

A low-cost and highly compact FPGA-based encryption/decryption architecture for AES algorithm

C Equihua, E Anides, JL García… - IEEE Latin America …, 2021 - ieeexplore.ieee.org
Nowadays, the design of ultra-compact area advanced encryption standard (AES)
architectures is highly demanded by the electronics industry since many of these …

Diffusion geometry derived keypoints and local descriptors for 3d deformable shape analysis

X Wang, M Bennamoun, F Sohel… - Journal of Circuits, Systems …, 2021 - World Scientific
Geometric analysis of three-dimensional (3D) surfaces with local deformations is a
challenging task, required by mobile devices. In this paper, we propose a new local feature …

Design and implementation of low power Advanced Encryption Standard cryptocore utilizing dynamic pipelined asynchronous model

ES Selvapriya, L Suganthi - Integration, 2023 - Elsevier
Abstract The Advanced Encryption Standard (AES) has added new dimension to
cryptography with its potentials of safeguarding the health care devices and systems. This …

A 4-stage pipelined architecture for point multiplication of binary huff curves

M Rashid, M Imran, AR Jafri… - Journal of Circuits …, 2020 - World Scientific
This work has proposed a 4-stage pipelined architecture to achieve an optimized throughput
over area ratio for point multiplication (PM) computation in binary huff curves (BHC) …