Temporal logic model checking involves checking the state-space of a model of a system to
determine whether errors can occur in the system. Often this involves checking …

This paper presents the overal structure, the design criteria, and the main features of the tool
box Uppaal. It gives a detailed user guide which describes how to use the various tools of …

Uppaal is a tool suite for automatic verification of safety and bounded liveness properties of
real-time systems modeled as networks of timed automata. It includes: a graphical interface …

Handbook of Knowledge Representation describes the essential foundations of Knowledge
Representation, which lies at the core of Artificial Intelligence (AI). The book provides an up …

Equivalence checking is a formal verification approach that consists in proving that two
programs or models are related modulo some equivalence relation, or that one is included …

Abstract We consider (unbounded) Timed Petri Nets (TPNs) where each token is equipped
with a real-valued clock representing the 'age'of the token. Each arc in the net is provided …

This paper describes how a network of interacting timed automata can be used to model,
analyze, and verify motion planning problems in a scenario with multiple robotic vehicles …

We study the trap depth requirement for the realization of an optical clock using atoms
confined in a lattice. We show that site-to-site tunneling leads to a residual sensitivity to the …

We provide a subclass of parametric timed automata (PTA) that we can actually and
efficiently analyze, and we argue that it retains most of the practical usefulness of PTA for the …

We present a framework for formal veri. cation of a realtime extension of UML statecharts.
For clarity, we restrict ourselves to a reasonable subset of the rich UML statechart model and …