The design of a 2.4-GHz fully integrated ΣΔ fractional-N frequency synthesizer in a 0.35-μm
CMOS process is presented. The design focuses on the prescaler and the loop filter, which …

A 900-MHz phase-locked loop frequency synthesizer implemented in a 0.6-/spl mu/m CMOS
technology is developed for the wireless integrated network sensors applications. It …

Current-Mode digital circuits have been extensively analyzed and used since the early days
of digital ICs. In particular, bipolar Current-Mode digital circuits emerged as an approach to …

Super-regeneration is re-examined for its simplicity and power efficiency for low-power,
short-range communication. A fully integrated super-regenerative receiver in 0.13-mum …

A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in
phase-locked systems. In this digital calibration technique, there is no extra replica CP …

The power consumption and operating frequency of the extended true single-phase clock (E-
TSPC)-based frequency divider is investigated. The short-circuit power and the switching …

A fully integrated CMOS direct-conversion 5-GHz transceiver with automatic frequency
control is implemented in a 0.18-μm digital CMOS process and housed in an LPCC-48 …

A CMOS phase-locked loop (PLL) which synthesizes frequencies between 6.336 and 8.976
GHz in steps of 528 MHz and settles in approximately 150 ns is presented. The proposed …

An LC-VCO based phase-locked loop (PLL) frequency synthesizer which incorporates loop
bandwidth tracking is described. In order to minimize loop bandwidth variations resulting …

A 5.2-GHz CMOS receiver employs a double downconversion heterodyne architecture with
a local oscillator frequency of 2.6 GHz and applies offset cancellation to the baseband …