A Two-Stage Interpolation Time-to-Digital Converter Implemented in 20 and 28 N· m FGPAs

Y Wang, W Xie, H Chen, C Pei… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
This article presents a two-stage interpolation time-to-digital converter (TDC), combining a
Vernier gray code oscillator TDC (VGCO-TDC) and a tapped-delay line TDC (TDL-TDC) …

Frontiers and challenges in silicon-based single-photon avalanche diodes and key readout circuits

Y Liu, L Wang, L Gao, R Fan, X Su, L Shen, S Pu… - Microelectronics …, 2024 - Elsevier
Single-photon detectors enable the detection of extremely weak light with remarkable
temporal precision. This capability provides crucial technological support for precise …

Design of a 3-bit 2.2 ps step 357.5 ps range 0.247 μm2 0.85 μW 45 nm All-MOS delay element

SM Sharroush, YS Abdalla - Integration, 2024 - Elsevier
The delay element is considered a very important component in various systems such as
microprocessors, memories, and delay-locked loops, to name such a few. Most of these …

[PDF][PDF] The Design of a Phase Interpolator

B Razavi - IEEE Solid-State Circuits Magazine, 2023 - seas.ucla.edu
Phase interpolators (PIs) find application in beamforming wireless systems and in wireline
transceivers. The latter typically employ PIs within their clock and data recovery (CDR) …

A high-performance time to digital converter for dToF LIDAR applications

L Chen, B Li, C Cheng - 2024 - researchsquare.com
As the resolution and conversion speed of Time-to-Digital Conversion (TDC) chips continue
to improve, the bit error rate also increases, leading to a decrease in the linearity of TDC and …

[引用][C] Low-power and high-precision SPAD array readout circuit based on built-in clock

Z Lixia, H Yongqi… - Infrared and …, 2023 - Editorial Office of Journal of Infrared …

[引用][C] 基于内置时钟的低功耗高精度SPAD 阵列读出电路

郑丽霞, 韩永奇, 万成功, 周谋昭… - Infrared and Laser …, 2023 - 红外与激光工程编辑部