Fan-out wafer-level packaging for heterogeneous integration

JH Lau, M Li, ML Qingqian, T Chen, I Xu… - IEEE Transactions …, 2018 - ieeexplore.ieee.org
The design, materials, process, fabrication, and reliability of a heterogeneous integration of
four chips and four capacitors by a fan-out wafer-level packaging (FOWLP) method are …

Fan-Out Wafer-Level Packaging for Heterogeneous Integration

JHS Lau, M Li, MQ Li, T Chen, I Xu… - IEEE Transactions on …, 2018 - repository.ust.hk
The design, materials, process, fabrication, and reliability of a heterogeneous integration of
four chips and four capacitors by a fan-out wafer-level packaging (FOWLP) method are …

[PDF][PDF] Fan-Out Wafer-Level Packaging for Heterogeneous Integration

JH Lau, M Li, ML Qingqian, T Chen, I Xu, QX Yong… - academia.edu
The design, materials, process, fabrication, and reliability of a heterogeneous integration of
four chips and four capacitors by a fan-out wafer-level packaging (FOWLP) method are …

[引用][C] Fan-Out Wafer-Level Packaging for Heterogeneous Integration

JH Lau, M Li, ML Qingqian, T Chen, I Xu… - IEEE Transactions on …, 2018 - cir.nii.ac.jp

Fan-Out Wafer-Level Packaging for Heterogeneous Integration

J Lau, M Li, M Li, T Chen, I Xu, QX Yong… - 2018 IEEE 68th …, 2018 - ieeexplore.ieee.org
The design, materials, process, fabrication, and reliability of a heterogeneous integration of
4 chips and 4 capacitors by a FOWLP (fan-out wafer-level packaging) method are …

[引用][C] Fan-Out Wafer-Level Packaging for Heterogeneous Integration

JH Lau, M Li, ML Qingqian, T Chen, I Xu… - Ieee Transactions …, 2018 - scholars.ntou.edu.tw
Fan-Out Wafer-Level Packaging for Heterogeneous Integration | National Taiwan Ocean
University Research Hub Skip navigation 中文 English DSpace CRIS DSpace logo 首頁 …

Fan-out wafer-level packaging for heterogeneous integration

JH Lau, M Li, M Li, T Chen, I Xu, QX Yong… - Proceedings …, 2018 - repository.ust.hk
The design, materials, process, fabrication, and reliability of a heterogeneous integration of
4 chips and 4 capacitors by a FOWLP (fan-out wafer-level packaging) method are …