Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs

R Das, S Eachempati, AK Mishra… - 2009 IEEE 15th …, 2009 - ieeexplore.ieee.org
Performance and power consumption of an on-chip interconnect that forms the backbone of
chip multiprocessors (CMPs), are directly influenced by the underlying network topology …
被引用次数：253 相关文章

Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs

R Das, S Eachempati, AK Mishra, V Narayanan… - 2009 IEEE 15th … - infona.pl
Performance and power consumption of an on-chip interconnect that forms the backbone of
chip multiprocessors (CMPs), are directly influenced by the underlying network topology …

Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs

R Das, S Eachempati, AK Mishra… - IEEE 15th International …, 2009 - pure.psu.edu
Performance and power consumption of an on-chip interconnect that forms the backbone of
Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology …

Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs

R Das, S Eachempati, AK Mishra, V Narayanan… - 2009 IEEE 15th … - infona.pl
Performance and power consumption of an on-chip interconnect that forms the backbone of
chip multiprocessors (CMPs), are directly influenced by the underlying network topology …