APPROX-NoC: A data approximation framework for network-on-chip architectures
The trend of unsustainable power consumption and large memory bandwidth demands in
massively parallel multicore systems, with the advent of the big data era, has brought upon …
massively parallel multicore systems, with the advent of the big data era, has brought upon …
Approximate communication strategies for energy-efficient and high performance NoC: Opportunities and challenges
With the advancement and miniaturization of transistor technology, hundreds of cores can
be integrated on a single chip. Network-on-Chips (NoCs) are the de facto on-chip …
be integrated on a single chip. Network-on-Chips (NoCs) are the de facto on-chip …
Learning-based quality management for approximate communication in network-on-chips
Current multi/many-core systems spend large amounts of time and power transmitting data
across on-chip interconnects. This problem is aggravated when data-intensive applications …
across on-chip interconnects. This problem is aggravated when data-intensive applications …
An approximate communication framework for network-on-chips
Current multi-/many-core systems spend large amounts of time and power transmitting data
across on-chip interconnects. This problem is aggravated when data-intensive applications …
across on-chip interconnects. This problem is aggravated when data-intensive applications …
DEC-NoC: An approximate framework based on dynamic error control with applications to energy-efficient NoCs
Network-on-Chips (NoCs) have emerged as the standard on-chip communication fabrics for
multi/many core systems and system on chips. However, as the number of cores on chip …
multi/many core systems and system on chips. However, as the number of cores on chip …
NoΔ: Leveraging delta compression for end-to-end memory access in NoC based multicores
As the number of on-chip processing elements increases, the interconnection backbone
bears bursty traffic from memory and cache accesses. In this paper, we propose a …
bears bursty traffic from memory and cache accesses. In this paper, we propose a …
DAPPER: Data aware approximate NoC for GPGPU architectures
VY Raparti, S Pasricha - 2018 Twelfth IEEE/ACM International …, 2018 - ieeexplore.ieee.org
High interconnect bandwidth is crucial to achieve better performance in many-core GPGPU
architectures that execute highly data parallel applications. The parallel warps of threads …
architectures that execute highly data parallel applications. The parallel warps of threads …
AxNoC: Low-power approximate network-on-chips using critical-path isolation
Various parallel applications, such as numerical convergent computation and multimedia
processing, have intrinsic tolerance to inaccuracies that allow soft errors, ie bit flips, on a …
processing, have intrinsic tolerance to inaccuracies that allow soft errors, ie bit flips, on a …
Performance and power optimization through data compression in network-on-chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for
larger on-chip caches. Such large caches are constructed as a multitude of smaller cache …
larger on-chip caches. Such large caches are constructed as a multitude of smaller cache …
Adaptive data compression for high-performance low-power on-chip networks
With the recent design shift towards increasing the number of processing elements in a chip,
high-bandwidth support in on-chip interconnect is essential for low-latency communication …
high-bandwidth support in on-chip interconnect is essential for low-latency communication …