We introduce a novel family of asymmetric dual-Vt SRAM cell designs that reduce leakage
power in caches while maintaining low access latency. Our designs exploit the strong bias …

A 6T static random access memory (SRAM) cell with a new write-assist (WA) feature is
presented. The WA technique reduces the problem of writing a" one" through an nMOS pass …

This paper presents the design and evaluation of a new SRAM cell made of nine transistors
(9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it is …

A 10T SRAM cell with data-independent bitline leakage and a virtual-ground replica scheme
allows 1k cells per bitline in subthreshold SRAMs. Reverse short-channel effect is used to …

Suppressing the leakage current in memories is critical in low-power design. By reducing
the standby supply voltage (V/sub DD/) to its limit, which is the data retention voltage (DRV) …

This brief introduces a differential eight-transistor static random access memory (SRAM) cell
for subthreshold SRAM applications. The symmetric topology offers a smaller area overhead …

A 4Mb SRAM is designed and fabricated on a 65nm CMOS technology. It features a 0.57/spl
mu/m/sup 2/6T cell with large noise margin down to 0.7 V for low-voltage operation. The fully …

Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for
transistors manufactured in very deep submicron regime. As a result, reducing the …

In high performance Systems-on-Chip, leakage power consumption has become
comparable to the dynamic component, and its relevance increases as technology scales …

In this paper, two static random access memory (SRAM) cells that reduce the static power
dissipation due to gate and subthreshold leakage currents are presented. The first cell …