Performance and power consumption of an on-chip interconnect that forms the backbone of
chip multiprocessors (CMPs), are directly influenced by the underlying network topology …

Until very recently, microprocessor designs were computation-centric. On-chip
communication was frequently ignored. This was because of fast, single-cycle on-chip …

This paper examines the area, power, performance, and design issues for the on-chip
interconnects on a chip multiprocessor, attempting to present a comprehensive view of a …

Interconnect networks play a critical role in shared memory multi-processor systems-on-chip
(MPSoC) designs. MPSoC performance and power consumption are greatly affected by the …

We study the space of chip multiprocessor (CMP) organizations. We compare the area and
performance trade-offs for CMP implementations to determine how many processing cores …

As demand for bandwidth increases in systems-on-a-chip and chip multiprocessors,
networks are fast replacing buses and dedicated wires as the pervasive interconnect fabric …

Many core chips are emerging as the architecture of choice to provide power efficiency and
improve performance, while riding Moore's Law. In these architectures, on-chip inter …

We develop detailed area and energy models for on-chip interconnection networks and
describe tradeoffs in the design of efficient networks for tiled chip multiprocessors. Using …

The paper introduces network-on-chip (NoC) design methodology and low cost mechanisms
for supporting efficient cache access and cache coherency in future high-performance chip …

As chip multiprocessors scale to a greater number of processing cores, on-chip
interconnection networks will experience dramatic increases in both bandwidth demand and …