In this paper, we present a hardware technique, called self-repairing array structures
(SRAS), for masking hard faults in microprocessor array structures, such as the reorder …

We present a self-repairing circuit for a mesh-connected processor array with faulty
processing elements which are directly replaced by spare processing elements on two …

Fault-tolerant based Systems Page 1 How do computers go wrong and what can we do about it?
This tutorial outlines the causes offaults and the basic techniquesfor dealing with them …

Device scaling trends dramatically increase the susceptibility of microprocessors to soft
errors. Further, mounting demand for embedded microprocessors in a wide array of safety …

Cache data errors read by a processor may cause CPU control flow error and force the
system to enter a CPU-cache reintegration process in redundant processor systems. The …

This paper speculates that technology trends pose new challenges for fault tolerance in
microprocessors. Specifically, severely reduced design tolerances implied by gigaherz clock …

This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of
providing error correction for SRAM caches. It is important to limit such overheads as …

This paper lays foundations for an approach to on-chip row/column allocation that exploits
certain properties offered by laterally connected networks of simple threshold devices. As a …

Protection against transient faults is an important constraint in high-performance processor
design. One strategy for achieving efficient reliability is to apply targeted fault …

Transient faults from neutron and alpha particle strikes in large SRAM caches have become
a major problem for microprocessor designers. To protect these caches, designers often use …