Tolerating hard faults in microprocessor array structures
In this paper, we present a hardware technique, called self-repairing array structures
(SRAS), for masking hard faults in microprocessor array structures, such as the reorder …
(SRAS), for masking hard faults in microprocessor array structures, such as the reorder …
A built-in circuit for self-repairing mesh-connected processor arrays by direct spare replacement
I Takanami, T Horita - 2012 IEEE 18th Pacific Rim International …, 2012 - ieeexplore.ieee.org
We present a self-repairing circuit for a mesh-connected processor array with faulty
processing elements which are directly replaced by spare processing elements on two …
processing elements which are directly replaced by spare processing elements on two …
Fault-tolerant microprocessor-based systems
B Johnson - IEEE Micro, 1984 - computer.org
Fault-tolerant based Systems Page 1 How do computers go wrong and what can we do about it?
This tutorial outlines the causes offaults and the basic techniquesfor dealing with them …
This tutorial outlines the causes offaults and the basic techniquesfor dealing with them …
Cost-efficient soft error protection for embedded microprocessors
Device scaling trends dramatically increase the susceptibility of microprocessors to soft
errors. Further, mounting demand for embedded microprocessors in a wide array of safety …
errors. Further, mounting demand for embedded microprocessors in a wide array of safety …
Fault-containment in cache memories for TMR redundant processor systems
Cache data errors read by a processor may cause CPU control flow error and force the
system to enter a CPU-cache reintegration process in redundant processor systems. The …
system to enter a CPU-cache reintegration process in redundant processor systems. The …
AR-SMT: A microarchitectural approach to fault tolerance in microprocessors
E Rotenberg - Digest of Papers. Twenty-Ninth Annual …, 1999 - ieeexplore.ieee.org
This paper speculates that technology trends pose new challenges for fault tolerance in
microprocessors. Specifically, severely reduced design tolerances implied by gigaherz clock …
microprocessors. Specifically, severely reduced design tolerances implied by gigaherz clock …
Memory mapped ECC: Low-cost error protection for last level caches
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of
providing error correction for SRAM caches. It is important to limit such overheads as …
providing error correction for SRAM caches. It is important to limit such overheads as …
Generation of minimal vertex covers for row/column allocation in self-repairable arrays
MD Smith, P Mazumder - IEEE transactions on computers, 1996 - ieeexplore.ieee.org
This paper lays foundations for an approach to on-chip row/column allocation that exploits
certain properties offered by laterally connected networks of simple threshold devices. As a …
certain properties offered by laterally connected networks of simple threshold devices. As a …
Assertion-based microarchitecture design for improved fault tolerance
VK Reddy, AS Al-Zawawi… - … Conference on Computer …, 2006 - ieeexplore.ieee.org
Protection against transient faults is an important constraint in high-performance processor
design. One strategy for achieving efficient reliability is to apply targeted fault …
design. One strategy for achieving efficient reliability is to apply targeted fault …
Cache scrubbing in microprocessors: Myth or necessity?
SS Mukherjee, J Emer, T Fossum… - 10th IEEE Pacific Rim …, 2004 - ieeexplore.ieee.org
Transient faults from neutron and alpha particle strikes in large SRAM caches have become
a major problem for microprocessor designers. To protect these caches, designers often use …
a major problem for microprocessor designers. To protect these caches, designers often use …