As the number of cores on a chip increases and key applications become even more data-
intensive, memory systems in modern processors have to deal with increasingly large …

This synthesis lecture presents the current state-of-the-art in applying low-latency, lossless
hardware compression algorithms to cache, memory, and the memory/cache link. There are …

This research explores a compressed memory hierarchy model which can increase both the
effective memory space and bandwidth of each level of memory hierarchy. It is well known …

As key applications become more data-intensive and the computational throughput of
processors increases, the amount of data to be transferred in modern memory subsystems …

The memory system's large and growing contribution to system performance motivates more
aggressive approaches to improving its efficiency. We propose and analyze a memory …

Memory compression has been proposed and deployed in the past to grow the capacity of a
memory system and reduce page fault rates. Compression also has secondary benefits: it …

Microprocessor designers have been torn between tight constraints on the amount of on-
chip cache memory and the high latency of off-chip memory, such as dynamic random …

In this paper we investigate the application of data compression to the main memory of
current workstation architectures. We propose an organisation where data and code are …

A new memory subsystem, called Memory Xpansion Technology (MXT), has been built for
compressing main memory contents. MXT effectively doubles the physically available …

Proposed cache compression schemes make design-time assumptions on value locality to
reduce decompression latency. For example, some schemes assume that common values …