Cache compression is a promising technique to increase on-chip cache capacity and to
decrease on-chip and off-chip bandwidth usage. Unfortunately, directly applying well-known …

Microprocessor designers have been torn between tight constraints on the amount of on-
chip cache memory and the high latency of off-chip memory, such as dynamic random …

Low utilization of on-chip cache capacity limits performance and wastes energy because of
the long latency, limited bandwidth, and energy consumption associated with off-chip …

Proposed cache compression schemes make design-time assumptions on value locality to
reduce decompression latency. For example, some schemes assume that common values …

In multicore processor systems, last-level caches (LLCs) play a crucial role in reducing
system energy by i) filtering out expensive accesses to main memory and ii) reducing the …

Cache compression seeks the benefits of a larger cache with the area and power of a
smaller cache. Ideally, a compressed cache increases effective capacity by tightly …

Modern processors use two or more levels ofcache memories to bridge the rising disparity
betweenprocessor and memory speeds. Compression canimprove cache performance by …

This research explores any potential for an on-chip cache compression which can reduce
not only cache miss ratio but also miss penalty, if main memory is also managed in …

Abstract Dynamic Zero Compression reduces the energy required for cache accesses by
only writing and reading a single bit for every zero-valued byte. This energy-conscious …

With the widening gap between processor and memory speeds, memory system designers
may find cache compression beneficial to increase cache capacity and reduce off-chip …