GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists
This work introduces a generic, machine learning (ML)-based platform for functional reverse
engineering (RE) of circuits. Our proposed platform GNN-RE leverages the notion of graph …
engineering (RE) of circuits. Our proposed platform GNN-RE leverages the notion of graph …
ReIGNN: State register identification using graph neural networks for circuit reverse engineering
SD Chowdhury, K Yang, P Nuzzo - 2021 IEEE/ACM …, 2021 - ieeexplore.ieee.org
Reverse engineering an integrated circuit netlist is a powerful tool to help detect malicious
logic and counteract design piracy. A critical challenge in this domain is the correct …
logic and counteract design piracy. A critical challenge in this domain is the correct …
Highway to HAL: open-sourcing the first extendable gate-level netlist reverse engineering framework
S Wallat, N Albartus, S Becker, M Hoffmann… - Proceedings of the 16th …, 2019 - dl.acm.org
Since hardware oftentimes serves as the root of trust in our modern interconnected world,
malicious hardware manipulations constitute a ubiquitous threat in the context of the Internet …
malicious hardware manipulations constitute a ubiquitous threat in the context of the Internet …
Reverse engineering digital circuits using structural and functional analyses
Integrated circuits (ICs) are now designed and fabricated in a globalized multivendor
environment making them vulnerable to malicious design changes, the insertion of …
environment making them vulnerable to malicious design changes, the insertion of …
Machine learning and structural characteristics for reverse engineering
J Baehr, A Bernardini, G Sigl… - … of the 24th Asia and South …, 2019 - dl.acm.org
In the past years, much of the research into hardware reverse engineering has focused on
the abstraction of gate level netlists to a human readable form. However, none of the …
the abstraction of gate level netlists to a human readable form. However, none of the …
ParaGraph: Layout parasitics and device parameter prediction using graph neural networks
H Ren, GF Kokai, WJ Turner… - 2020 57th ACM/IEEE …, 2020 - ieeexplore.ieee.org
Layout-dependent parasitics and device parameters significantly impact integrated circuit
performance and are often the cause of slow convergences between schematic and layout …
performance and are often the cause of slow convergences between schematic and layout …
CktGNN: Circuit graph neural network for electronic design automation
The electronic design automation of analog circuits has been a longstanding challenge in
the integrated circuit field due to the huge design space and complex design trade-offs …
the integrated circuit field due to the huge design space and complex design trade-offs …
Functionality matters in netlist representation learning
Learning feasible representation from raw gate-level netlists is essential for incorporating
machine learning techniques in logic synthesis, physical design, or verification. Existing …
machine learning techniques in logic synthesis, physical design, or verification. Existing …
Deepgate2: Functionality-aware circuit representation learning
Circuit representation learning aims to obtain neural repre-sentations of circuit elements and
has emerged as a promising research direction that can be applied to various EDA and logic …
has emerged as a promising research direction that can be applied to various EDA and logic …
Versatile multi-stage graph neural network for circuit representation
Due to the rapid growth in the scale of circuits and the desire for knowledge transfer from old
designs to new ones, deep learning technologies have been widely exploited in Electronic …
designs to new ones, deep learning technologies have been widely exploited in Electronic …