A case for dynamic frequency tuning in on-chip networks
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that
have become the de-facto standard in providing scalable communication backbones for …
have become the de-facto standard in providing scalable communication backbones for …
A case for heterogeneous on-chip interconnects for CMPs
Network-on-chip (NoC) has become a critical shared resource in the emerging Chip
Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across …
Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across …
iDEAL: Inter-router dual-function energy and area-efficient links for network-on-chip (NoC) architectures
AK Kodi, A Sarathy, A Louri - ACM SIGARCH Computer Architecture …, 2008 - dl.acm.org
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core
designs as a flexible and scalable solution to the increasing wire delay constraints in the …
designs as a flexible and scalable solution to the increasing wire delay constraints in the …
Extending the energy efficiency and performance with channel buffers, crossbars, and topology analysis for network-on-chips
D DiTomaso, R Morris, AK Kodi… - IEEE transactions on …, 2012 - ieeexplore.ieee.org
Network-on-chips (NoCs) have emerged as a scalable solution to the wire delay constraints,
thereby providing a high-performance communication fabric for future multicores. Research …
thereby providing a high-performance communication fabric for future multicores. Research …
[图书][B] Efficient microarchitecture for network-on-chip routers
DU Becker - 2012 - search.proquest.com
Continuing advances in semiconductor technology, coupled with an increasing concern for
energy efficiency, have led to an industry-wide shift in focus towards modular designs that …
energy efficiency, have led to an industry-wide shift in focus towards modular designs that …
Agile: A learning-enabled power and performance-efficient network-on-chip design
A number of techniques to achieve power-efficient Network-on-Chips (NoCs) have been
proposed, two of which are power-gating and dynamic voltage and frequency scaling …
proposed, two of which are power-gating and dynamic voltage and frequency scaling …
Improving DVFS in NoCs with coherence prediction
As Networks-on-Chip (NoCs) continue to consume a large fraction of the total chip power
budget, dynamic voltage and frequency scaling (DVFS) has evolved into an integral part of …
budget, dynamic voltage and frequency scaling (DVFS) has evolved into an integral part of …
Dynamic voltage and frequency scaling in NoCs with supervised and reinforcement learning techniques
Network-on-Chips (NoCs) are the de facto choice for designing the interconnect fabric in
multicore chips due to their regularity, efficiency, simplicity, and scalability. However, NoC …
multicore chips due to their regularity, efficiency, simplicity, and scalability. However, NoC …
Fine-grained bandwidth adaptivity in networks-on-chip using bidirectional channels
Networks-on-Chip (NoC) serve as efficient and scalable communication substrates for many-
core architectures. Currently, the bandwidth provided in NoCs is over provisioned for their …
core architectures. Currently, the bandwidth provided in NoCs is over provisioned for their …
Next generation on-chip networks: What kind of congestion control do we need?
In this paper, we present network-on-chip (NoC) design and contrast it to traditional network
design, highlighting core differences between NoCs and traditional networks. As an initial …
design, highlighting core differences between NoCs and traditional networks. As an initial …