A high performance split-radix FFT with constant geometry architecture
J Kwong, M Goel - 2012 Design, Automation & Test in Europe …, 2012 - ieeexplore.ieee.org
High performance hardware FFTs have numerous applications in instrumentation and
communication systems. This paper describes a new parallel FFT architecture which …
communication systems. This paper describes a new parallel FFT architecture which …
A novel low-power and in-place split-radix FFT processor
Z Qian, M Margala - Proceedings of the 24th edition of the great lakes …, 2014 - dl.acm.org
Split-radix Fast Fourier Transform (SRFFT) approximates the minimum number of
multiplications by theory among all the FFT algorithms. Since multiplications significantly …
multiplications by theory among all the FFT algorithms. Since multiplications significantly …
FPGA implementation of low-power split-radix FFT processors
Fast Fourier Transform (FFT) is one of the fundamental operations in digital signal
processing area. Split-radix Fast Fourier Transform (SRFFT) approximates the minimum …
processing area. Split-radix Fast Fourier Transform (SRFFT) approximates the minimum …
Low-power split-radix FFT processors using radix-2 butterfly units
Z Qian, M Margala - IEEE Transactions on Very Large Scale …, 2016 - ieeexplore.ieee.org
Split-radix fast Fourier transform (SRFFT) is an ideal candidate for the implementation of a
low-power FFT processor, because it has the lowest number of arithmetic operations among …
low-power FFT processor, because it has the lowest number of arithmetic operations among …
Radix-4 FFT implementation using SIMD multimedia instructions
K Nadehara, T Miyazaki, I Kuroda - 1999 IEEE International …, 1999 - ieeexplore.ieee.org
A fast radix-4 complex FFT implementation using 4-parallel SIMD instructions is presented.
Four radix-4 butterflies are calculated in parallel at all stages by loading consecutive 4 …
Four radix-4 butterflies are calculated in parallel at all stages by loading consecutive 4 …
A low-power twiddle factor addressing architecture for split-radix FFT processor
M Liu, P Zhao, T Wu, KK Parhi, X Zeng, Y Chen - Microelectronics Journal, 2021 - Elsevier
The split-radix fast Fourier transform (SRFFT) is attractive for low-power FFT processors as it
has the lowest numbers of multiplication operations among all FFT algorithms. FFT …
has the lowest numbers of multiplication operations among all FFT algorithms. FFT …
A family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communications
A Suleiman, H Saleh, A Hussein… - 2008 IEEE International …, 2008 - ieeexplore.ieee.org
The paper presents a family of architectures for FFT implementation based on the
decomposition of the perfect shuffle permutation, which can be designed with variable …
decomposition of the perfect shuffle permutation, which can be designed with variable …
Optimized hardware implementation of fft processor
AA Al Sallab, H Fahmy… - 2009 4th International …, 2009 - ieeexplore.ieee.org
Fast Fourier transform (FFT) is an essential component in many digital signal processing
and communications systems. The performance of the FFT component is a key factor in …
and communications systems. The performance of the FFT component is a key factor in …
High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit
In this paper we propose a fully parallel 64K point radix-4 4 FFT processor. The radix-4 4
parallel unrolled architecture uses a novel radix-4 butterfly unit which takes all four inputs in …
parallel unrolled architecture uses a novel radix-4 butterfly unit which takes all four inputs in …
A pipeline architecture for modified higher radix FFT
E Bernard, JG Krammer, M Sauer… - … ] ICASSP-92: 1992 …, 1992 - ieeexplore.ieee.org
A method, called twiddle-factor-shift, which combines the simplicity of interconnections and
processor elements (PEs) of radix-2 fast Fourier transform (FFT) algorithms and of the lower …
processor elements (PEs) of radix-2 fast Fourier transform (FFT) algorithms and of the lower …