Node-covering based defect and fault tolerance methods for increased yield in FPGAs
F Hanchek, S Dutt - … of 9th International Conference on VLSI …, 1996 - ieeexplore.ieee.org
Fault tolerant techniques are proposed which make use of the reconfigurability of SRAM-
based field programmable gate arrays (FPGAs). Based on the principle of node-covering, a …
based field programmable gate arrays (FPGAs). Based on the principle of node-covering, a …
[PDF][PDF] The Teramac Custom Computer: Extending the Limits with Defect Tolerance.
WB Culbertson, R Amerson, RJ Carter, P Kuekes… - dft, 1996 - Citeseer
Teramac is a reconfigurable custom computer, capable of running million-gate user designs
at one megahertz and out-performing workstations a hundred-fold on highly parallel …
at one megahertz and out-performing workstations a hundred-fold on highly parallel …
Timing driven placement reconfiguration for fault tolerance and yield enhancement in FPGAs
A Mathur, CL Liu - Proceedings ED&TC European Design and …, 1996 - ieeexplore.ieee.org
The architectural regularity of FPGAs provides an inherent redundancy which can be
exploited for fault tolerance and yield enhancement. In this paper we examine the problem …
exploited for fault tolerance and yield enhancement. In this paper we examine the problem …
Making defect avoidance nearly invisible to the user in wafer scale field programmable gate arrays
GH Chapman, B Dufort - … on Defect and Fault Tolerance in VLSI …, 1996 - ieeexplore.ieee.org
Field programmable gate arrays have the main features required for interesting wafer scale
systems: high flexibility with potential large number of applications, a repeatable cell, and a …
systems: high flexibility with potential large number of applications, a repeatable cell, and a …
[引用][C] Detailed-Routability of FPGAs with Extremal Switch-Block Structures
YTATY KAJITANI - Proceedings, 1996 - IEEE Computer Society Press