Speed and Power Scaling of SRAM's
BS Amrutur, MA Horowitz - IEEE journal of solid-state circuits, 2000 - ieeexplore.ieee.org
Simple models for the delay, power, and area of a static random access memory (SRAM) are
used to determine the optimal organizations for an SRAM and study the scaling of their …
used to determine the optimal organizations for an SRAM and study the scaling of their …
[PDF][PDF] Highly-associative caches for low-power processors
M Zhang, K Asanovic - Kool Chips Workshop, 33rd International …, 2000 - groups.csail.mit.edu
Since caches consume a significant fraction of total processor energy, eg, 43% for
StrongARM-1 [8], many studies have investigated energy-efficient cache designs [1, 5, 12 …
StrongARM-1 [8], many studies have investigated energy-efficient cache designs [1, 5, 12 …
A low-power SRAM with resonantly powered data, address, word, and bit lines
N Tzartzanis, W Athas… - Proceedings of the 26th …, 2000 - ieeexplore.ieee.org
We present a low-power SRAM based on resonantly powered data-in, data-out, address,
word, and bit lines. The clock rails power these lines from a two-phase resonant driver. The …
word, and bit lines. The clock rails power these lines from a two-phase resonant driver. The …
[PDF][PDF] Copper Interconnects for High-Speed, Low-Power Static Memories
A Sinha, S Singh, A Ajami, AR Ahmed… - Semiconductor …, 2000 - researchgate.net
1 University of Southern California-Information Sciences Institute 4676 Admiralty Way,
Marina del Rey, CA 90292 Abstract: The effect of copper interconnects on memories is …
Marina del Rey, CA 90292 Abstract: The effect of copper interconnects on memories is …