An embedded 32-b microprocessor core for low-power and high-performance applications
LT Clark, EJ Hoffman, J Miller, M Biyani… - IEEE Journal of solid …, 2001 - ieeexplore.ieee.org
An embedded RISC microprocessor core fabricated in a six-layer metal 0.18-/spl mu/m
CMOS process implementing the ARM/sup TM/V. 5TE instruction set is described. The core …
CMOS process implementing the ARM/sup TM/V. 5TE instruction set is described. The core …
Fast low-power decoders for RAMs
BS Amrutur, MA Horowitz - IEEE Journal of Solid-State Circuits, 2001 - ieeexplore.ieee.org
Decoder design involves choosing the optimal circuit style and figuring out their sizing,
including adding buffers if necessary. The problem of sizing a simple chain of logic gates …
including adding buffers if necessary. The problem of sizing a simple chain of logic gates …
Universal-V/sub dd/0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell
K Osada, JL Shin, M Khan, Y Liou… - IEEE Journal of Solid …, 2001 - ieeexplore.ieee.org
A universal-V/sub dd/32-kB four-way-set-associative embedded cache has been developed.
A test cache chip was fabricated by using 0.18-/spl mu/m enhanced CMOS technology, and …
A test cache chip was fabricated by using 0.18-/spl mu/m enhanced CMOS technology, and …
Duplicate bitline self-time technique for reliable memory operation
JUL Shin, K Osada, M Khan - US Patent 6,212,117, 2001 - Google Patents
Broadly, the present invention provides a duplicate col umn of bit cells, a predetermined
number of which are set to a predetermined State and coupled together So that they are all …
number of which are set to a predetermined State and coupled together So that they are all …
A localized self-resetting gate design methodology for low power
WJ Kim, YB Kim - Proceedings of the 44th IEEE 2001 Midwest …, 2001 - ieeexplore.ieee.org
In this paper, a modification of the traditional dynamic self-reset circuitry is introduced for low
power SRAM circuit design. The reset circuitry is localized, and the negative (trailing) trigger …
power SRAM circuit design. The reset circuitry is localized, and the negative (trailing) trigger …
Ultra-Low-Voltage Memory Circuits
K Itoh, K Itoh - VLSI Memory Chip Design, 2001 - Springer
The reduction of the operating voltage is essential not only to reduce power dissipation, but
also to ensure reliablity for miniaturized devices. Further reduction of the supply voltage …
also to ensure reliablity for miniaturized devices. Further reduction of the supply voltage …
Neural network modeling study of one dimension gray problem GNNM (1, 1)
H Song, B Han - 2001 International Conferences on Info-Tech …, 2001 - ieeexplore.ieee.org
The study on representing and processing uncertain information is an important subject in
information era. This paper combines gray system with neural network in processing one …
information era. This paper combines gray system with neural network in processing one …