This paper reviews recent important results in the development of neuromorphic network
architectures ('CrossNets') for future hybrid semiconductor/nanodevice‐integrated circuits. In …

In this paper, we present a hardware technique, called self-repairing array structures
(SRAS), for masking hard faults in microprocessor array structures, such as the reorder …

Asynchronous cellular arrays have gained attention as promising architectures for
nanocomputers, because of their lack of a clock, which facilitates low power designs, and …

We present a design methodology for a nanoscale self-assembling fabrication process that
uses the specificity of DNA hybridization to guide the formation of electrical circuitry. Custom …

This work presents a novel architecture, which is both device and circuit independent. The
starting idea is that computations can be performed in three fundamentally different ways …

This paper explores the architectural challenges introduced by emerging bottom-up
fabrication of nanoelectronic circuits and develops an architecture that meets these …

Motivated by the need for cost-effective fault-tolerant nano architectures, we explore von
Neumann multiplexing (vN-MUX) at small and very small redundancy factors. We present a …

New varieties of computer architectures, capable of solving highly demanding computational
problems, are enabled by the large manufacturing scale expected from self-assembling …

Computing systems implemented with nanotechnology will need to employ defect-and fault-
tolerant measures to improve their reliability due to the large number of factors that may lead …

Parallel processors such as SIMD computers have been successfully used in various areas
of high performance image and data processing. Due to their characteristics of highly …