Neuromorphic architectures for nanoelectronic circuits
Ö Türel, JH Lee, X Ma… - International Journal of …, 2004 - Wiley Online Library
This paper reviews recent important results in the development of neuromorphic network
architectures ('CrossNets') for future hybrid semiconductor/nanodevice‐integrated circuits. In …
architectures ('CrossNets') for future hybrid semiconductor/nanodevice‐integrated circuits. In …
Tolerating hard faults in microprocessor array structures
In this paper, we present a hardware technique, called self-repairing array structures
(SRAS), for masking hard faults in microprocessor array structures, such as the reorder …
(SRAS), for masking hard faults in microprocessor array structures, such as the reorder …
Fault-tolerance in nanocomputers: a cellular array approach
Asynchronous cellular arrays have gained attention as promising architectures for
nanocomputers, because of their lack of a clock, which facilitates low power designs, and …
nanocomputers, because of their lack of a clock, which facilitates low power designs, and …
The design of DNA self-assembled computing circuitry
C Dwyer, L Vicci, J Poulton, D Erie… - IEEE transactions on …, 2004 - ieeexplore.ieee.org
We present a design methodology for a nanoscale self-assembling fabrication process that
uses the specificity of DNA hybridization to guide the formation of electrical circuitry. Custom …
uses the specificity of DNA hybridization to guide the formation of electrical circuitry. Custom …
A novel highly reliable low-power nano architecture when von Neumann augments Kolmogorov
V Beiu - Proceedings. 15th IEEE International Conference on …, 2004 - ieeexplore.ieee.org
This work presents a novel architecture, which is both device and circuit independent. The
starting idea is that computations can be performed in three fundamentally different ways …
starting idea is that computations can be performed in three fundamentally different ways …
[PDF][PDF] Circuit and system architecture for DNA-guided self-assembly of nanoelectronics
This paper explores the architectural challenges introduced by emerging bottom-up
fabrication of nanoelectronic circuits and develops an architecture that meets these …
fabrication of nanoelectronic circuits and develops an architecture that meets these …
Multiplexing schemes for cost-effective fault-tolerance
S Roy, V Beiu - 4th IEEE Conference on Nanotechnology, 2004 …, 2004 - ieeexplore.ieee.org
Motivated by the need for cost-effective fault-tolerant nano architectures, we explore von
Neumann multiplexing (vN-MUX) at small and very small redundancy factors. We present a …
Neumann multiplexing (vN-MUX) at small and very small redundancy factors. We present a …
DNA self-assembled parallel computer architectures
C Dwyer, J Poulton, R Taylor, L Vicci - Nanotechnology, 2004 - iopscience.iop.org
New varieties of computer architectures, capable of solving highly demanding computational
problems, are enabled by the large manufacturing scale expected from self-assembling …
problems, are enabled by the large manufacturing scale expected from self-assembling …
Nanocomputing in the presence of defects and faults: A survey
P Graham, M Gokhale - … quantum and molecular computing: Implications to …, 2004 - Springer
Computing systems implemented with nanotechnology will need to employ defect-and fault-
tolerant measures to improve their reliability due to the large number of factors that may lead …
tolerant measures to improve their reliability due to the large number of factors that may lead …
From massively parallel image processors to fault-tolerant nanocomputers
Parallel processors such as SIMD computers have been successfully used in various areas
of high performance image and data processing. Due to their characteristics of highly …
of high performance image and data processing. Due to their characteristics of highly …