Reliability analysis of large circuits using scalable techniques and tools
The rapid development of CMOS and non-CMOS nanotechnologies has opened up new
possibilities and introduced new challenges for circuit design. One of the main challenges is …
possibilities and introduced new challenges for circuit design. One of the main challenges is …
Comparing reliability-redundancy tradeoffs for two von Neumann multiplexing architectures
Nanoelectronic systems are anticipated to be highly susceptible to computation and
communication noise. Interestingly, von Neumann addressed the issue of computation in the …
communication noise. Interestingly, von Neumann addressed the issue of computation in the …
Serial addition: Locally connected architectures
V Beiu, S Aunet, J Nyathi, RR Rydberg… - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
This paper will briefly review nanoelectronic challenges while focusing on reliability. We
shall present and analyze a series of CMOS-based examples for addition starting from the …
shall present and analyze a series of CMOS-based examples for addition starting from the …
Fault tolerant structures for nanoscale gates
F Martorell, SD Cotofana… - 2007 7th IEEE Conference …, 2007 - ieeexplore.ieee.org
Predicted device reliability for nanoelectronics indicates that redundant design will be
necessary to build reliable nanosystems. Up to date, several fault tolerant techniques have …
necessary to build reliable nanosystems. Up to date, several fault tolerant techniques have …
A fresh look at majority multiplexing when devices get into the picture
In this paper we present the first detailed analysis of von Neumann multiplexing (vN-MUX)
using majority (MAJ) gates of small fan-ins Δ (MAJ-Δ) with respect to the probability of failure …
using majority (MAJ) gates of small fan-ins Δ (MAJ-Δ) with respect to the probability of failure …
Probabilistic maximum error modeling for unreliable logic circuits
K Lingasubramanian, S Bhanja - Proceedings of the 17th ACM Great …, 2007 - dl.acm.org
Reliability modeling and evaluation is expected to be one of the major issues in emerging
nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for …
nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for …
Defect tolerance based on coding and series replication in transistor-logic demultiplexer circuits
W Robinett, PJ Kuekes… - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
We present a family of defect tolerant transistor-logic demultiplexer circuits that can defend
against both stuck-ON (short defect) and stuck-OFF (open defect) transistors. Short defects …
against both stuck-ON (short defect) and stuck-OFF (open defect) transistors. Short defects …
Towards nanoelectronics processor architectures
In this paper, we focus on reliability, one of the most fundamental and important challenges,
in the nanoelectronics environment. For a processor architecture based on the unreliable …
in the nanoelectronics environment. For a processor architecture based on the unreliable …
[图书][B] Fehlertolerante neuronale Netze zur Approximation von Funktionen
R Eickhoff - 2007 - core.ac.uk
Aufgrund neuster Erkenntnisse in den kognitiven Wissenschaften und dem
Biologieingenieurwesen ist es möglich, die Funktionsweise und die Zusammenhänge in …
Biologieingenieurwesen ist es möglich, die Funktionsweise und die Zusammenhänge in …
Thermal noise informatics: totally secure communication via a wire, zero-power communication, and thermal noise driven computing
Very recently, it has been shown that Gaussian thermal noise and its artificial versions
(Johnson-like noises) can be utilized as an information carrier with peculiar properties …
(Johnson-like noises) can be utilized as an information carrier with peculiar properties …