Digital circuit design challenges and opportunities in the era of nanoscale CMOS
Well-designed circuits are one key ldquoinsulatingrdquo layer between the increasingly
unruly behavior of scaled complementary metal-oxide-semiconductor devices and the …
unruly behavior of scaled complementary metal-oxide-semiconductor devices and the …
[图书][B] CMOS SRAM circuit design and parametric test in nano-scaled technologies: process-aware SRAM design and test
As technology scales into nano-meter region, design and test of Static Random Access
Memories (SRAMs) becomes a highly complex task. Process disturbances and various …
Memories (SRAMs) becomes a highly complex task. Process disturbances and various …
Numerical estimation of yield in sub-100-nm SRAM design using Monte Carlo simulation
H Nho, SS Yoon, SS Wong… - IEEE Transactions on …, 2008 - ieeexplore.ieee.org
This paper describes a method to numerically calculate the design margin and to estimate
the yield associated with the read access failure for sub-100-nm SRAM. Process variations …
the yield associated with the read access failure for sub-100-nm SRAM. Process variations …
Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines
A configurable replica bitline (cRBL) technique for controlling sense-amplifier enable (SAE)
timing for small-swing bitline SRAMs is described. Post-silicon selection of a subset of …
timing for small-swing bitline SRAMs is described. Post-silicon selection of a subset of …
A methodology for statistical estimation of read access yield in SRAMs
MH Abu-Rahma, K Chowdhury, J Wang… - Proceedings of the 45th …, 2008 - dl.acm.org
The increase of process variations in advanced CMOS technologies is considered one of
the biggest challenges for SRAM designers. This is aggravated by the strong demand for …
the biggest challenges for SRAM designers. This is aggravated by the strong demand for …
A resilient and power-efficient automatic-power-down sense amplifier for SRAM design
YC Lai, SY Huang - IEEE Transactions on Circuits and Systems …, 2008 - ieeexplore.ieee.org
A conventional latch-type sense amplifier in a static random access memory (SRAM) could
trigger sensing failure under severe process variation. On the other hand, a traditional …
trigger sensing failure under severe process variation. On the other hand, a traditional …
Stability and static noise margin analysis of low-power SRAM
R Keerthi, CH Chen - 2008 IEEE Instrumentation and …, 2008 - ieeexplore.ieee.org
To overcome the read data destruction and to gain stability at Iow-V DD a seven-transistor
(7T) SRAM cell is implemented and compared with the conventional six-transistor (6T) …
(7T) SRAM cell is implemented and compared with the conventional six-transistor (6T) …
Hybrid-mode SRAM sense amplifiers: New approach on transistor sizing
D Anh-Tuan, K Zhi-Hui… - IEEE Transactions on …, 2008 - ieeexplore.ieee.org
A novel high-speed sense amplifier for ultra-low-voltage SRAM applications is presented. It
introduces a completely different way of sizing the aspect ratio of the transistors on the data …
introduces a completely different way of sizing the aspect ratio of the transistors on the data …
Wide Embedded Asynchronous SRAM With Dual-Mode Self-Timed Technique for Dynamic Voltage Systems
MF Chang, SM Yang, KT Chen - IEEE Transactions on Circuits …, 2008 - ieeexplore.ieee.org
Voltage-dependent timing skews in precharge and sensing activities cause functional failure
and reduce the speed of asynchronous static random-access memory (SRAM). Data …
and reduce the speed of asynchronous static random-access memory (SRAM). Data …
A 100MHz to 1GHz, 0.35 v to 1.5 v supply 256 x 64 SRAM block using symmetrized 9T SRAM cell with controlled read
SA Verkila, SK Bondada… - … Conference on VLSI …, 2008 - ieeexplore.ieee.org
In this paper, we present dynamic voltage and frequency Managed 256 x 64 SRAM block in
65 nm technology, for frequency ranging from 100 MHz to 1 GHz. The total energy is …
65 nm technology, for frequency ranging from 100 MHz to 1 GHz. The total energy is …