Overview and outlook of through‐silicon via (TSV) and 3D integrations
JH Lau - Microelectronics International, 2011 - emerald.com
Purpose–The purpose of this paper is to focus on through‐silicon via (TSV), with a new
concept that every chip or interposer could have two surfaces with circuits. Emphasis is …
concept that every chip or interposer could have two surfaces with circuits. Emphasis is …
Evolution, challenge, and outlook of TSV, 3D IC integration and 3D silicon integration
JH Lau - … symposium on advanced packaging materials (APM), 2011 - ieeexplore.ieee.org
3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They
are different and in general the TSV (through-silicon via) separates 3D IC packaging from …
are different and in general the TSV (through-silicon via) separates 3D IC packaging from …
The most cost-effective integrator (TSV interposer) for 3D IC integration system-in-package (SiP)
JH Lau - International Electronic Packaging …, 2011 - asmedigitalcollection.asme.org
The significant roles of Cu-filled TSV passive interposers for 3D IC integration are
investigated in this study. Emphasis is placed on the roles they play as:(1) substrates;(2) …
investigated in this study. Emphasis is placed on the roles they play as:(1) substrates;(2) …
Wire-bonded through-silicon vias with low capacitive substrate coupling
AC Fischer, M Grange, N Roxhed… - Journal of …, 2011 - iopscience.iop.org
Three-dimensional integration of electronics and/or MEMS-based transducers is an
emerging technology that vertically interconnects stacked dies with through-silicon vias …
emerging technology that vertically interconnects stacked dies with through-silicon vias …
Effects of TSV interposer on the reliability of 3D IC integration SiP
The effect of Cu-filled through-silicon vias (TSVs) interposers on the reliability of 3D IC
integration system-in-package (SiP) is investigated in this study. Emphasis is placed on the …
integration system-in-package (SiP) is investigated in this study. Emphasis is placed on the …
TSV interposers with embedded microchannels for 3D IC and LED integration
A low-cost (with bare chips), high cooling ability and very low pressure drop 3D IC
integration system-in-package (SiP) is designed and described. This system consists of a …
integration system-in-package (SiP) is designed and described. This system consists of a …
Wafer level led interposer
GS Kim, JJ Kim, YM Koo - US Patent App. 13/098,625, 2011 - Google Patents
A wafer level LED interposer and its manufacturing method is provided. The wafer level LED
interposer includes: a LED chip of which N-type electrode and p-type electrode are formed …
interposer includes: a LED chip of which N-type electrode and p-type electrode are formed …