In this paper, the innovations in device design of the gate-all-around (GAA) nanosheet FET
are reviewed. These innovations span enablement of multiple threshold voltages and …

This work performs a detailed comparison of the channel width folding effectiveness of the
FinFET, vertically stacked nanosheet transistor (VNSFET), and vertically stacked nanowire …

A comprehensive computational study of gate-all-around (GAA) devices with 3-D stacked
silicon nanosheets (also known as nanoribbons or nanowires) is presented in this article …

This paper proposes a simplified fabrication processing for nanosheet Field-Effect
Transistors (FETs) part of beyond-3-nm node technology. Formation of the ground plane …

The potential for negative-capacitance field-effect transistors (NCFETs) to enhance the unity-
current-gain cutoff frequency and ratio through a technique that mitigates the impacts of …

Junctionless complementary field effect transistor (JL-CFET) is an emerging device that
needs a small layout area and low fabrication cost. However, in order for the JL-CFET to be …

An on-wafer micro-detector for in situ EUV (wavelength of 13.5 nm) detection featuring
FinFET CMOS compatibility, 1 T pixel and battery-less sensing is demonstrated. Moreover …

In this work, WS2 was adopted as a channel material among transition metal
dichalcogenides (TMD) materials that have recently been in the spotlight, and the circuit …

We present a predictive process design kit (PDK) for the 5 nm technology node, the ASAP5
PDK. ASAP5 is not related to a particular foundry and the assumptions are derived from …

Room-temperature (RT) thermodynamics of a dopant-atom double quantum dot (DQD)
silicon transistor are extracted using measurements of the dual gate charge stability …