A high-performance, resource-efficient, reconfigurable parallel-pipelined FFT processor for FPGA platforms
The fast Fourier transform (FFT) algorithm is widely used in digital signal processing systems
(DSPs); hence, the development of a high-performance and resource-efficient FFT …
(DSPs); hence, the development of a high-performance and resource-efficient FFT …
[HTML][HTML] Alternate computation of the unit vectors synthesis towards synchronization of current-controlled grid-tie converter for renewable power system: An embedded …
A Maiti, P Syam, K Mukherjee - Engineering Science and Technology, an …, 2022 - Elsevier
Phase synchronization and frequency tracking are essential part of control unit design for
the grid-tie power converter of the efficient energy conversion system. A robust but …
the grid-tie power converter of the efficient energy conversion system. A robust but …
A novel method for computing exponential function using cordic algorithm
J Sudha, MC Hanumantharaju, V Venkateswarulu… - Procedia …, 2012 - Elsevier
In this paper, design of Coordinate Rotation Digital Computer (CORDIC) based 2D
Gaussian function and an efficient Very Large Scale Integration (VLSI) architecture suitable …
Gaussian function and an efficient Very Large Scale Integration (VLSI) architecture suitable …
Improved parameterized efficient FPGA implementations of parallel 1-D filtering algorithms using Xilinx System Generator
S Hasan, S Boussakta… - The 10th IEEE International …, 2010 - ieeexplore.ieee.org
Two hardware architectures are developed via an improved parameterized efficient FPGA
implementation method for parallel 1-D real-time signal filtering algorithms to provide higher …
implementation method for parallel 1-D real-time signal filtering algorithms to provide higher …
A dsPIC based novel digital sinusoidal pulse-width modulation technique for voltage source inverter applications
A Datta, D Mukherjee, H Saha - Microprocessors and Microsystems, 2014 - Elsevier
This paper presents a novel digital sinusoidal pulse-width modulation (SPWM) technique
based on immediate calculation of duty cycle count (DCC) values of pulses with high speed …
based on immediate calculation of duty cycle count (DCC) values of pulses with high speed …
[PDF][PDF] 高速高精度固定角度旋转CORDIC 算法的设计与实现
张朝柱， 韩吉南， 燕慧智 - 电子学报, 2016 - ejournal.org.cn
固定角度旋转的CORDIC (Coordinate Rotation Digital Computer) 算法已经广泛的应用于高速
数字信号处理, 图像处理, 机器人学等领域. 针对固定角度旋转CORDIC 算法在相位旋转过程中 …
数字信号处理, 图像处理, 机器人学等领域. 针对固定角度旋转CORDIC 算法在相位旋转过程中 …
Design of 32-bits RISC processor for hardware efficient QR decomposition
SS Omran, AK Abdul-abbas - 2018 International Conference on …, 2018 - ieeexplore.ieee.org
The QR decomposition (QRD) is an implementation prerequisite for many different detection
algorithms in MIMO (multiple-input multiple-output) wisely communication system. In this …
algorithms in MIMO (multiple-input multiple-output) wisely communication system. In this …
全定制CORDIC 运算器设计
毕〓卓戴益君 - 计算机工程与科学, 2011 - joces.nudt.edu.cn
浮点三角函数计算是导航系统, 三维图像处理, 雷达信号预处理等领域的基本运算.
本文采用CORDIC 算法及全定制集成电路设计方法实现了一种浮点三角函数计算电路 …
本文采用CORDIC 算法及全定制集成电路设计方法实现了一种浮点三角函数计算电路 …
FPGA implementation of a matrix structure for integer division
BC Alecsa, AD Ioan - 2010 3rd International Symposium on …, 2010 - ieeexplore.ieee.org
This paper presents a method for fast, parallel matrix implementation of an integer division
algorithm inside FPGA that can be used for real-time control systems. An essential …
algorithm inside FPGA that can be used for real-time control systems. An essential …
Noise degradation system using Wiener filter and CORDIC based FFT/IFFT processor
A Yasodai, AV Ramprasad - Journal of Central South University, 2015 - Springer
On augmentation of past work, an effective Wiener filter and its application for noise
suppression combined with a formed CORDIC based FFT/IFFT processor with improved …
suppression combined with a formed CORDIC based FFT/IFFT processor with improved …