A NoC-based simulator for design and evaluation of deep neural networks

KCJ Chen, M Ebrahimi, TY Wang, YC Yang… - Microprocessors and …, 2020 - Elsevier
The astonishing development in the field of artificial neural networks (ANN) has brought
significant advancement in many application domains, such as pattern recognition, image …

Efficient design-for-test approach for networks-on-chip

J Wang, M Ebrahimi, L Huang, X Xie… - IEEE Transactions …, 2018 - ieeexplore.ieee.org
To achieve high reliability in on-chip networks, it is necessary to test the network
continuously with Built-in Self-Tests (BIST) so that the faults can be detected quickly and the …

Fast and cycle-accurate emulation of large-scale networks-on-chip using a single fpga

TV Chu, S Sato, K Kise - ACM Transactions on Reconfigurable …, 2017 - dl.acm.org
Modeling and simulation/emulation play a major role in research and development of novel
Networks-on-Chip (NoCs). However, conventional software simulators are so slow that …

Visual Exploratory Analysis for Designing Large-Scale Network-on-Chip Architectures: A Domain Expert-Led Design Study

S Wang, H Yan, KE Isaacs, Y Sun - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Visualization design studies bring together visualization researchers and domain experts to
address yet unsolved data analysis challenges stemming from the needs of the domain …

FPGA friendly NoC simulation acceleration framework employing the hard blocks

BMP Prasad, K Parane, B Talawar - Computing, 2021 - Springer
A major role is played by Modeling and Simulation platforms in development of a new
Network-on-Chip (NoC) architecture. The cycle accurate software simulators tend to become …

Component Dependencies Based Network-on-Chip Test

L Huang, T Zhao, Z Wang, J Zhan… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
On-line test of NoC is essential for its reliability. This paper proposed an integral test solution
for on-line test of NoC to reduce the test cost and improve the reliability of NOC. The test …

A lifetime-aware mapping algorithm to extend MTTF of networks-on-chip

L Huang, S Chen, Q Wu, M Ebrahimi… - 2018 23rd Asia and …, 2018 - ieeexplore.ieee.org
Fast aging of components has become one of the major concerns in Systems-on-Chip with
further scaling of the submicron technology. This problem accelerates when combined with …

A Lego-Based Neural Network Design Methodology With Flexible NoC

KC Chen, CK Tsai, YS Liao, HB Xu… - IEEE Journal on …, 2021 - ieeexplore.ieee.org
Deep Neural Networks (DNNs) have shown superiority in solving the problems of
classification and recognition in recent years. However, DNN hardware implementation is …

Optimizing dynamic mapping techniques for on-line NoC test

S Jiang, Q Wu, S Chen, J Wang… - 2018 23rd Asia and …, 2018 - ieeexplore.ieee.org
With the aggressive scaling of submicron technology, intermittent faults are becoming one of
the limiting factors in achieving a high reliability in Network-on-Chip (NoC). Increasing test …

Testing aware dynamic mapping for path-centric network-on-chip test

S Jiang, Q Wu, S Chen, J Zhan, J Wang, M Ebrahimi… - Integration, 2019 - Elsevier
With the aggressive scaling of submicron technology, intermittent faults are becoming one of
the limiting factors in achieving high reliability in Network-on-Chip (NoC). Increasing test …