Aggressive technology scaling makes modern advanced SRAMs more and more vulnerable
to soft errors such as single-node upsets (SNUs) and double-node upsets (DNUs). This …

Artificial intelligence (AI) has revolutionized present-day life through automation and
independent decision-making capabilities. For AI hardware implementations, the 6T-SRAM …

This paper proposes a highly robust 16 transistor soft-error resilient SRAM cell (SERSC-
16T) to provide complete resilience to single event upsets (SEU). The proposed cell is …

With technology scaling, transistor sizing as well as the distance between them, is
decreasing rapidly, thereby reducing the critical charge of sensitive nodes. This reduction …

The static random access memory (SRAM) cells are essential for aerospace applications in
near sub-threshold voltage, and it has challenges for the implementation of SRAM cells for …

This paper presents radiation hardened SRAM (namely LPDNUR and HSDNUR), both of
which can self-recover from single-node and double-node upsets. LPDNUR uses a two …

SRAM cells in spacecraft or space stations are susceptible to single event upset (SEU)
caused by high-energy particle impacts. Conventional 6 T SRAM cells are more prone to soft …

Static random access memory (SRAM) is a critical cell of VLSI, which is sensitive to the
charge generated by high-energy particles and susceptible to logical errors. In this paper …

As the CMOS technology continues to shrink, latches are becoming increasingly susceptible
to multiple-node-upset caused by charge sharing in radiation environments. In this paper, a …

This paper proposes a novel design of ultra-low power radiation-hardened single-ended
SRAM bit-cell using the gate-all-around CNT-MOSFET based-gate diffusion input method …