Soft error rates for triple-well and dual-well SRAM circuits over the past few technology
generations have shown an apparently inconsistent behavior. This work compares the …

With the decrease of the device size, soft error induced by various particles becomes a
serious problem for advanced CMOS technologies. In this paper, we review the evolution of …

Heavy ion, neutron, and laser experimental data are used to evaluate the effectiveness of
various single event latchup (SEL) hardening strategies, including silicon-on-insulator (SOI) …

FinFET, with narrow silicon fin, and high k/metal gate stacked combined with SOI technology
brings benefits to radiation effects. Single event transient (SET) of SOI FinFET at 14 nm …

Heavy ion experiments on 65 nm bulk CMOS inverter chains demonstrate the impact of
circuit placement on single-event transients (SETs). Experimental data and simulations …

The standard and layout-hardened D filp-flops (DFFs) named DFF1-6 were designed and
manufactured based on an advanced 22-nm ultrathin body and buried oxide fully depleted …

Background........................................................................................................................... 46 Neutron-
induced SEL in dual and triple well SRAMs.......................................................... 49 Laser …

Silicon-on-insulator technology is often used to develop high-reliability devices with low
sensitivity to single-event upsets or soft errors. Its key component, the buried-oxide (BOX) …

In this article, we present a new method to mitigate the effect of the charge collected by
trigate FinFET devices after an ionizing particle impact. The method is based on the creation …

Three layout-hardened Dual Interlocked Storage Cell (DICE) D Flip-Flops (DFFs) were
designed and manufactured based on an advanced 28 nm planar technology. The …