This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …

A logic circuit is said to be combinational if the function it computes depends only on the
inputs applied to the circuit, and is sequential if it depends on some past history in addition …

Single-rail handshake circuits are introduced as a cost effective implementation of
asynchronous circuits. Compared to double-rail implementations, the circuits are smaller …

We propose a false-path-aware statistical timing analysis framework. In our framework, cell
as well as interconnect delays are assumed to be correlated random variables. Our tool can …

Recently published results have shown that, for many circuits, only a small percentage of
path delay faults is robust testable, Among the robust untestable faults, a significant …

Applications that are co-scheduled on a multi-core compete for shared resources, such as
cache capacity and memory bandwidth. The performance degradation resulting from this …

In this paper, we present logic optimization techniques for multilevel combinational
networks. Our techniques apply a sequence of perturbations which result in simplification of …

Recently published results have shown that, for many circuits, only a small percentage of
path delay faults is robust testable. Among the robust untestable faults, a significant …

This paper addresses the problem of estimating human gaze from eye appearance under
free head motion. Allowing head motion remains challenging because eye appearance …

In nanometric integrated circuits, to harden reliability-critical gates (RCGs) is an important
step to improve overall circuit reliability at a low cost. To locate RCGs quickly and efficiently …