This paper presents Mr. Wolf, a parallel ultra-low power (PULP) system on chip (SoC)
featuring a hierarchical architecture with a small (12 kgates) microcontroller (MCU) class …

Gain-cell embedded DRAM (GC-eDRAM) is a possible alternative to traditional static
random access memories (SRAM). While GC-eDRAM provides high-density, low-leakage …

This article presents a deep neural network (DNN) accelerator using an adaptive clocking
technique (ie, elastic clock chain) to exploit the dynamic timing margin for the 2-D …

This paper presents an instruction-driven adaptive clock management scheme using a
dynamic phase scaling (DPS) operation and compiler-assisted cross-layer design …

Cycle-by-cycle dynamic timing slack (DTS), which represents extra timing margin from the
critical-path timing slack reported by the static timing analysis (STA), has been observed at …

This brief presents the unique capabilities of the multimode Dual Mode Logic (DML) design
technique to define run-time adaptive datapaths to overcome process and environmental (ie …

Computing latency is an important system metric for Deep Neural Networks (DNNs)
accelerators. To reduce latency, this work proposes LV, a latency-versatile floating-point …

Dynamic timing slack has emerged as a compelling opportunity for eliminating inefficiency in
ultra-low power embedded systems. This slack arises when all the signals have propagated …

This paper presents an adaptive clock phase scaling operation based on the dynamic
instruction timing variation for a low power microprocessor. Through the use of instruction …

Machine learning algorithms such as Convolutional Neural Networks (CNNs) are
characterized by high robustness towards quantization, supporting small-bitwidth fixed-point …