Challenges and emerging solutions in testing TSV-based 2 1 over 2D-and 3D-stacked ICs
EJ Marinissen - 2012 Design, Automation & Test in Europe …, 2012 - ieeexplore.ieee.org
Through-Silicon Vias (TSVs) provide high-density, low-latency, and low-power vertical
interconnects through a thinned-down wafer substrate, thereby enabling the creation of 2.5 …
interconnects through a thinned-down wafer substrate, thereby enabling the creation of 2.5 …
Yield enhancement for 3D-stacked ICs: Recent advances and challenges
Three-dimensional (3D) integrated circuits (ICs) that stack multiple dies vertically using
through-silicon vias (TSVs) have gained wide interests of the semiconductor industry. The …
through-silicon vias (TSVs) have gained wide interests of the semiconductor industry. The …
Fault and self-repair for high reliability in die-to-die interconnection of 2.5 D/3D IC
R Song, J Zhang, Z Zhu, G Shan, Y Yang - Microelectronics Reliability, 2024 - Elsevier
Bringing dies closer by die-to-die interconnection is a way that reduces latency and energy
per bit transmitted, while increasing bandwidth per mm of chip. Heterogeneous integration …
per bit transmitted, while increasing bandwidth per mm of chip. Heterogeneous integration …
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs
Three-dimensional (3D) integration using through silicon via (TSV) has been widely
acknowledged as one future integrated-circuit (IC) technology. A 3D IC including multiple …
acknowledged as one future integrated-circuit (IC) technology. A 3D IC including multiple …
IEEE Std P1838: DfT standard-under-development for 2.5 D-, 3D-, and 5.5 D-SICs
EJ Marinissen, T McLaurin… - 2016 21th IEEE european …, 2016 - ieeexplore.ieee.org
For stacked integrated circuits, effective test access requires the design-for-test (DfT)
features in the various dies to operate in a concerted way to transport test stimuli and …
features in the various dies to operate in a concerted way to transport test stimuli and …
Post-bond testing of 2.5 D-SICs and 3D-SICs containing a passive silicon interposer base
CC Chi, EJ Marinissen, SK Goel… - 2011 IEEE International …, 2011 - ieeexplore.ieee.org
Through-Silicon Vias (TSVs) enable high-density, low-latency, and low-power interconnects
for system chips that consist of multiple dies. In “2.5 D” Stacked ICs (2.5 D-SICs), multiple …
for system chips that consist of multiple dies. In “2.5 D” Stacked ICs (2.5 D-SICs), multiple …
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks
S Deutsch, B Keller, V Chickermane… - 2012 IEEE …, 2012 - ieeexplore.ieee.org
Three-dimensional (3D) die stacking is an emerging integration technology which brings
benefits with respect to heterogeneous integration, inter-die interconnect density …
benefits with respect to heterogeneous integration, inter-die interconnect density …
Challenges in testing TSV-based 3D stacked ICs: Test flows, test contents, and test access
EJ Marinissen - 2010 IEEE Asia Pacific Conference on Circuits …, 2010 - ieeexplore.ieee.org
Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) have many
attractive benefits and hence are quickly gaining ground. Testing such products for …
attractive benefits and hence are quickly gaining ground. Testing such products for …
TSV extracted equivalent circuit model and an on-chip test solution
Z Gong, R Rashidzadeh - IEEE Transactions on Computer …, 2015 - ieeexplore.ieee.org
Through silicon via (TSV) is the enabling technology for 3-D integrated circuit (IC)
realization. To develop manufacturing tests for 3-D ICs, TSV has to be accurately modeled …
realization. To develop manufacturing tests for 3-D ICs, TSV has to be accurately modeled …
Heterogeneous 3D integration—Technology enabler toward future super-chip
M Koyanagi - 2013 IEEE International Electron Devices …, 2013 - ieeexplore.ieee.org
To overcome various concerns caused by scaling-down the device size, it is indispensable
to introduce a new concept of heterogeneous 3D integration called a super-chip in which …
to introduce a new concept of heterogeneous 3D integration called a super-chip in which …