An efficient high throughput FPGA implementation of AES for multi-gigabit protocols

U Hussain, H Jamal - 2012 10th International Conference on …, 2012 - ieeexplore.ieee.org
Due to the requirement of high throughput architecture for encrypted channels, an efficient
implementation of hardware is needed. This can be achieved by using smart utilization of …

[PDF][PDF] Fpga-based real-time implementation of aes algorithm for video encryption

S Kotel, M Zeghid, A Baganne, T Saidani… - Recent Advances in …, 2014 - academia.edu
Multimedia data security is becoming an important concern due to the fact that multimedia
applications affect many aspects of our life. To deal with the increasing use of multimedia in …

Secure Video and Telemetry FPGA Architecture For UAVs

D Psilias, A Milidonis, G Lentaris… - 2024 9th South-East …, 2024 - ieeexplore.ieee.org
Unmanned Aerial Vehicles (UAVs) are used in a wide range of applications. However, since
they are vulnerable to cyberattacks security protocols for their data are used. Common …

[PDF][PDF] Design and Hardware Implementation of QoSS-AES Processor for Multimedia applications.

Z Medien, M Machhout, B Bouallegue, L Khriji… - Trans. Data Priv., 2010 - tdp.cat
For real-time applications, there are several factors (time, cost, power) that are moving
security considerations from a function centric perspective into a system architecture …

[图书][B] Studies on high-speed hardware implementation of cryptographic algorithms

K Järvinen - 2008 - aaltodoc.aalto.fi
Cryptographic algorithms are ubiquitous in modern communication systems where they
have a central role in ensuring information security. This thesis studies efficient …

Efficient hybrid encryption system based on block cipher and chaos generator

S Kotel, F Sbiaa, M Zeghid, M Machhout… - … on Computer and …, 2016 - ieeexplore.ieee.org
In recent years, more and more multimedia data are generated and transmitted in various
fields. So, many encryption methods for multimedia content have been put forward to satisfy …

基于HLS 技术的Rijndael 算法IP 核实现与优化

孙桂玲, 纪永鑫, 张潺潺, 李维祥 - 微电子学与计算机, 2010 - journalmc.com
为了降低传统设计模式在应对大规模SoC 设计时带来高复杂度, 使用高层次综合HLS
技术进行了Rijndael 算法IP 核的设计, 综合与仿真. 针对Rijndael 算法中的多种运算模块 …

Dynamically reconfigurable encryption system of the AES

W Youren, W Li, Y Rui, Z Zhai, C Jiang - Wuhan University Journal of …, 2006 - Springer
Reconfigurable computing has grown to become an important and large field of research, it
offers advantages over traditional hardware and software implementations of computational …

Dimensionnement et intégration d'un chiffre symétrique dans le contexte d'un système d'information distribué de grande taille.

T Roche - 2010 - theses.hal.science
L'évolution des architectures de systèmes d'information n'a de cesse depuis l'avènement
des télécommunications. Pour s' adapter aux nouvelles dimensions en nombre d'utilisateurs …

Implementation of HSSec: a High–Speed Cryptographic Co-Processor

AP Kakarountas, H Michail, CE Goutis… - … IEEE Conference on …, 2007 - ieeexplore.ieee.org
In this paper a high-speed cryptographic coprocessor, named HSSec, is presented. The
core embeds two hash functions, SHA-1 and SHA-512, and the symmetric block cipher AES …